Commit Graph

23 Commits

Author SHA1 Message Date
YRabbit
85e8570a73 gowin: handle the GW1N-9 feature.
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-04-03 10:05:27 +10:00
YRabbit
be8d3fd74d gowin: Consider the peculiarity of GW1BR-9C
The GW1NR-9C chip ODDR implementation differs from all other supported
chips by two suspicious inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-26 20:56:30 +10:00
Pepijn de Vos
bb923c7732
Gowin: use global VCC and VSS nets (#956)
* use global VCC and VSS nets

* derp

* remove init parameter
2022-03-19 18:44:08 +00:00
YRabbit
badef293eb gowin: add support for ODDR primitive
Compatible with older versions of apicula bases.
Also small fixes and as the number of virtual Bels grows it is necessary
to assign them Z coordinate in a centralized way to avoid conflicts and
for this purpose introduced the BelZ enum.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-15 11:02:37 +10:00
YRabbit
4a2aa6deb4 gowin: Add the Global Set/Reset primitive
GSR is added automatically if it was not instantiated by the user explicitly.

Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-12 23:05:42 +10:00
gatecat
86699b42f6 Switch to potentially-sparse net users array
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-27 13:47:05 +00:00
YRabbit
ad49b7c78d gowin: Add support for true differential output
The new primitive appears as an amalgamation of two existing OBUF
primitives.  Compatible with older versions of apicula, although, of
course, using TLVDS_OBUF with old databases will not bring the desired
result, but no crash.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-23 15:53:04 +10:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 17:09:54 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
YRabbit
5a76b3cb4d gowin: Add simplified IO cells processing
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input.  This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.

For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).

The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-12-20 15:48:38 +10:00
gatecat
a933f82845 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-12 18:49:37 +00:00
YRabbit
e0ab7bf6c1 gowin: BUGFIX. Place the ALU head in sliсe 0 only
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-12-11 19:10:02 +10:00
YRabbit
e9f3946d58 gowin: Explicitly initialize the y in the cluster
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-22 23:27:36 +10:00
YRabbit
f52fd6a272 gowin: Add ALU support.
- Both the mode used by yosys and all Gowin primitive modes are supported.
  - The ALU always starts with a zero slice.
  - The maximum length of the ALU chain is limited to one line of the chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-22 14:41:18 +10:00
YRabbit
c72ea15472 gowin: add support for wide LUTs.
* A hardwired MUX within each logical cell is used.
  * The delay is equal 0.
  * No user placement constraints.
  * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 18:38:33 +10:00
YRabbit
23a5e91858 gowin: Add constraints on primitive placement.
Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-08-31 07:36:11 +10:00
YRabbit
3f959c7421 gowin: Change the constraint parser to support multiple options per line. Add support for IOBUF and TBUF I/O modes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-08-06 17:43:20 +10:00
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
David Shah
818faa78aa clangformat
Signed-off-by: David Shah <dave@ds0.me>
2020-12-30 16:49:55 +00:00
Pepijn de Vos
3611f54902
Gowin target (#542)
* load wires

* add slice bels

* add IOB

* add aliases

* local aliases

* broken packing stuff

* working packer

* add constraints

* pnr runs1111

* add timing info

* constraints

* more constraint stuff

* add copyright

* remove generic reference

* remove parameters

* remove generic python api

* add newline to end of file

* some small refactoring

* warn on invalid constraints

* don't error on missing cell

* comment out debugging print

* typo

* avoid copy

* faster empty idstring

* remove intermediate variable

* no more deadnames

* fix cst warnings

* increase ripup and epsilon a bit

* take single device parameter

* add info to readme

* gui stubs

* Revert 4d03b681a8

* assign ff_used in assignArchInfo

* decrease beta for better routability

* try to fix CI
2020-12-30 14:59:55 +00:00