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Author SHA1 Message Date
whitequark
7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Eddie Hung
20f0353f76 Add report to attosoc_tb.vhd 2018-12-02 15:41:30 -08:00
Eddie Hung
b1b8183967 Re-enable PLL in attosoc.v 2018-12-02 15:41:03 -08:00
Eddie Hung
8f0e888815 nextpnr now writes to log, netgen to overwrite 2018-12-02 15:40:20 -08:00
Eddie Hung
5aff7bbbc4 Fix INIT of pass-thru LUT to be "2" not "1" 2018-12-02 15:32:29 -08:00
David Shah
6e728c9a9b
Merge pull request #160 from dmsc/sb_ledda_ip 
ice40: Add support for placing SB_LEDDA_IP block.
 2018-12-02 08:48:58 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block. 
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
 2018-12-01 22:27:04 -03:00
David Shah
dc549cd56b
Merge pull request #159 from YosysHQ/ecp5_pllplace 
ecp5: Pre-place PLLs and use dedicated routes into globals
 2018-12-01 09:14:34 +00:00
Eddie Hung
5ddfc32c75 Add attosoc.sh and attosoc_tb.vhd 2018-11-30 17:06:55 -08:00
Eddie Hung
4574a57efc Add attosoc 2018-11-30 15:24:32 -08:00
Eddie Hung
fdca3d6d77 firmware.hex with delay loop 2018-11-30 15:23:09 -08:00
David Shah
5ddf99cf5d ecp5: Pre-place PLLs and use dedicated routes into globals 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-30 16:09:56 +00:00
Eddie Hung
cac7ce2747 Cleanup 2018-11-29 17:20:51 -08:00
Eddie Hung
f4e7f4e690 Use wholesale attrs from ISE for MMCME2_ADV 2018-11-29 17:20:35 -08:00
Eddie Hung
2fdf937259 Assignment LUT inputs from fastest down 2018-11-29 17:08:05 -08:00
Eddie Hung
0327fa554a Revert "Ahead of LUT input swapping, assign LUT<6 from A6 downwards" 
This reverts commit ec96897c1d.
 2018-11-29 16:54:33 -08:00
Eddie Hung
c5165f7830 Duplicate arcs.clear() 2018-11-29 16:32:33 -08:00
Eddie Hung
d7dd945f55 Overwrite COMPENSATION attribute on MMCME2_ADV to "INTERNAL" 2018-11-29 16:32:08 -08:00
Eddie Hung
d8b6b231de Move required attributes to pack 2018-11-29 15:38:28 -08:00
Eddie Hung
6985e80c01 Merge branch 'xc7' of gitlab.com:eddiehung/nextpnr into xc7 2018-11-29 13:32:32 -08:00
Miodrag Milanovic
535fc953d4 Use site x location to determine if it is one block or other 2018-11-29 12:44:02 -08:00
Eddie Hung
9f03d9eed3 Add PLL to bring 125MHz clock to 60MHz for picorv32 2018-11-29 12:25:39 -08:00
David Shah
58e9c6f32e
Merge pull request #158 from YosysHQ/improve_error 
Error reporting improvements
 2018-11-29 19:46:05 +00:00
David Shah
8af367ad0a ice40: Add a warning for unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:35:19 +00:00
David Shah
90138fc120 rulecheck: Improve message printed at start 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:28:15 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
dbc14ea76d json: Improve reporting of multiple drivers 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:20:51 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh 
ice40: raise CE global promotion threshold
 2018-11-29 09:12:47 +00:00
David Shah
3ff3b0f6b5
Merge pull request #156 from whitequark/fanout 
ice40: print fanout of nets promoted to globals
 2018-11-29 09:08:40 +00:00
Eddie Hung
4161856d49 Add support for MMCME2_ADV 2018-11-28 22:34:22 -08:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
Miodrag Milanovic
bfa2157ae6 compile fix for gui and proper size 2018-11-28 17:59:58 +01:00
David Shah
0872b63b0b
Merge pull request #155 from smunaut/issue_151 
ice40: Update the way LVDS inputs are handled during bitstream generation
 2018-11-28 16:20:36 +00:00
David Shah
48071e3650
Merge pull request #154 from smunaut/issue_141 
ice40: Complete rework of the way PLLs are placed and validity checks
 2018-11-28 16:20:26 +00:00
Miodrag Milanovic
f2fecc3c69 make gui run 2018-11-28 17:04:26 +01:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation 
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:23 +01:00
David Shah
7a2ef27d6c
Merge pull request #153 from YosysHQ/global-options 
ice40: Finer-grained control of global promotion
 2018-11-28 07:43:00 +00:00
Eddie Hung
13e7798b34 Fix #endif placement 2018-11-27 18:11:19 -08:00
Eddie Hung
212b03999b Gzip the torc_info data 2018-11-27 18:08:03 -08:00
Eddie Hung
440802bf9d Add support for serialization of torc_info 2018-11-27 17:55:31 -08:00
Eddie Hung
662733c171 Remove methods 2018-11-27 14:12:25 -08:00
Eddie Hung
a0b6d3b19b clangformat 2018-11-27 12:28:48 -08:00
Eddie Hung
ae9ccfa5ad Refactor torc_info constructor 2018-11-27 12:28:21 -08:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
David Shah
e99e2f1570
Merge pull request #152 from YosysHQ/compile_fix 
Fix compile on GCC 5.5 or older
 2018-11-27 18:32:24 +00:00
Miodrag Milanovic
0b5748a7af Fix compile on GCC 5.5 or older 2018-11-27 19:20:15 +01:00
Eddie Hung
664c48f5e4 Merge https://github.com/YosysHQ/nextpnr into xc7 2018-11-27 09:45:35 -08:00