Commit Graph

5 Commits

Author SHA1 Message Date
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange.
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
e138a6c56d Do some spell checking on site_router.cc
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:34:06 -08:00
Keith Rothman
4766e889c0 Add some utility methods for site instance access.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:26:52 -08:00
Keith Rothman
c385321248 Add initial site router.
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00