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4,431 Commits 22 Branches 7 Tags 17 MiB
a0ba9afcba
Commit Graph

153 Commits

Author SHA1 Message Date
Miodrag Milanovic
a0ba9afcba CCU2D is auto tied low 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
aacb36bf15 Use CCU2D cell 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a00f810093 fix 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6f85053b03 more like ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
3624fe90b2 one step closer 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6508a0c267 This should not be here 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
153144022f More of making it inline 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ca3d32e5ac make source more inline with ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
62ace58204 add missing bind and lutperm 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7f8518d938 Import lutperm data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
442142a47a typo fixes 2023-05-04 14:23:08 +02:00
Lofty
398b2ab569 bitstream emission update 2023-05-04 14:23:08 +02:00
Lofty
235a575267 port ecp5 split slice to machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
b033b915a6 Add bitgen for the rest of XO2 and XO3 2023-05-04 14:23:08 +02:00
Lofty
89c71bc8ac bitstream fixes for xo3 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
80705e9bbb Support enabling XO3 and XO3D 2023-05-04 14:23:08 +02:00
gatecat
6455b5dd26 viaduct: Add support for GUIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-11 19:11:54 +02:00
Miodrag Milanovic
35eeaa7cc5 Add ramaining PIO tiles 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
3f4c8d15d9 Use unified io location data 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
0ce72e1a31 Use TRELLIS primitives 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
ad5f6fccaa Use RelSlice, make more in line with ecp5 arch 2023-03-20 09:53:35 +01:00
gatecat
e4fcd3740d cmake: Make HeAP placer always-enabled 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 10:38:11 +01:00
gatecat
4111cc25d6 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 09:31:38 +01:00
Miodrag Milanovic
11a90aff83 Fix out of tree builds and place h in generated 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
f008d7c4d8 Let top tiles be on top 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
6eb5f2a77e Enable wires and add dummy wire type for now 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
1f115ddd32 Basic GUI part selection 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
26798038fe Fix examples 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
7ad9914e51 Extend chipdb with metadata 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
d5b5f7e4b2 add new field handling in chip config format 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
4396a646a7 Add simple BEL graphics 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
18ad718e53 Expand list of possible devices 2023-03-16 13:37:23 +01:00
Lofty
52b02f7377 machxo2: Fix Python bindings for pip iterators 2023-02-13 12:49:00 +00:00
gatecat
7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
William D. Jones
064b6d808e clangformat. 2021-12-16 17:09:29 -05:00
William D. Jones
4d75792257 machxo2: Remove no-iobs option. It was always enabled and should remain an implementation detail. 2021-12-16 16:59:38 -05:00
William D. Jones
be3788fa30 machxo2: Remove -noiopad option when generating miters for post-pnr verification. 2021-12-16 16:59:38 -05:00
William D. Jones
365a871908 machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports. 2021-12-16 16:59:38 -05:00
William D. Jones
d2ac6dffbc machxo2: Correct which PIO wires get adjusted when writing text bitstream. Add verbose logging for adjustments. 2021-12-16 16:59:37 -05:00
William D. Jones
41d09f7187 machxo2: Fix packing for directly-connected DFFs. 2021-07-01 09:59:53 -04:00