David Shah
|
df79d94944
|
ecp5: DELAY fixes
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
95a85c8ea7
|
ecp5: Improve packing density
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
a0fa164399
|
ecp5: Add criticality-based LUT permutation
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
f363dd2d3c
|
ecp5: Delay tuning
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
4ec2bd1e5d
|
ecp5: Fix global clock routing with multiclock DPRAM
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
55b0b60d9d
|
ecp5: Router performance improvements
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
f5b11ce075
|
ecp5: Implement budget overrides for carry chains and SLICE muxes
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
af3ff143be
|
ecp5: Improve delay model
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
998d055ea7
|
ecp5: Speed up timing analysis
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-25 11:49:25 +00:00 |
|
David Shah
|
68abcb365a
|
ecp5: Add ECLKSYNCB support
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-24 10:28:25 +01:00 |
|
David Shah
|
52d1954d96
|
ecp5: Packing of ODDRX2F
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-24 10:28:25 +01:00 |
|
David Shah
|
63e1f02c65
|
ecp5: Helper functions for DQS and ECLK
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-24 10:28:25 +01:00 |
|
David Shah
|
db1666fc3d
|
ecp5: Add timing data for DQS-related cells
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-24 10:28:25 +01:00 |
|
Miodrag Milanović
|
c52202233a
|
Merge branch 'master' into mmaped_chipdb
|
2019-02-12 18:53:20 +01:00 |
|
David Shah
|
565d5eed17
|
ecp5: Fix global routing performance
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-12 10:56:17 +00:00 |
|
Miodrag Milanovic
|
73f200fe74
|
Load chipdb from filesystem as option
|
2019-02-09 13:34:57 +01:00 |
|
David Shah
|
e929d221f3
|
ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG
Signed-off-by: David Shah <dave@ds0.me>
|
2019-02-08 12:34:22 +00:00 |
|
David Shah
|
c01bb88509
|
ecp5: Add IOLOGIC timing and bitstream; ODDR working
Signed-off-by: David Shah <dave@ds0.me>
|
2018-12-14 16:40:38 +00:00 |
|
David Shah
|
4e05d09397
|
Improve reporting of unknown cell types
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-29 19:26:23 +00:00 |
|
David Shah
|
3ae8b86003
|
ecp5: Adding mux support up to LUT6
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 17:27:23 +00:00 |
|
David Shah
|
1ae722272a
|
ecp5: clangformat timing changes
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:27:03 +00:00 |
|
David Shah
|
50b85da619
|
ecp5: Use speed-grade-specific delay estimate
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:26:28 +00:00 |
|
David Shah
|
13244e513b
|
ecp5: Fix db import, improve timing data debugging
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:26:28 +00:00 |
|
David Shah
|
ffe1166e33
|
ecp5: Post-rebase fix
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:26:28 +00:00 |
|
David Shah
|
3ecd440748
|
ecp5: Use new timing data
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:26:28 +00:00 |
|
David Shah
|
18813f2056
|
ecp5: Adding real timing data to database
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-16 13:26:28 +00:00 |
|
David Shah
|
02736d0680
|
ecp5: Add timing info for SERDES
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
e9fe444dc7
|
ecp5: Adding ancillary DCU bels
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
c5a3571a06
|
ecp5: Working on DCU
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
Eddie Hung
|
2d39cde17b
|
Merge remote-tracking branch 'origin/master' into timingapi
|
2018-11-13 12:12:11 -08:00 |
|
Eddie Hung
|
3b2b15dc4a
|
Merge pull request #107 from YosysHQ/router_improve
Major rewrite of "router1"
|
2018-11-13 11:39:51 -08:00 |
|
David Shah
|
959d163ba7
|
ecp5: Improve delay estimates
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-13 14:27:23 +00:00 |
|
David Shah
|
11579a1046
|
ecp5: EBR clocking fix
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
8af86ff37d
|
ecp5: Update arch to new timing API
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
Miodrag Milanovic
|
0ad5197ff4
|
show 4th tresllis_io in tile bounds
|
2018-11-11 08:25:54 +01:00 |
|
David Shah
|
e005cc6754
|
ecp5: Add PLL support
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 19:52:41 +00:00 |
|
David Shah
|
1a06f4b2bd
|
ecp5: Adding DSP support
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 20:07:18 +01:00 |
|
David Shah
|
b5faa7ad10
|
ecp5: Implement ECP5 equivalent of c9059fc
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 17:15:34 +01:00 |
|
David Shah
|
1cde208090
|
clangformat
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:58 +01:00 |
|
David Shah
|
8aac6db44b
|
ecp5: Add support for correct tile naming in all variants
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:24 +01:00 |
|
David Shah
|
3aa3f5d796
|
ecp5: Add DP16KD timing analysis
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 13:30:23 +01:00 |
|
David Shah
|
19f828c91c
|
ecp5: Dummy timing entry for BRAM
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 11:35:37 +01:00 |
|
David Shah
|
9ebec3b87f
|
clangformat
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 18:20:14 +01:00 |
|
David Shah
|
3dfc5b864a
|
ecp5: Remove broken DRAM timing arc
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 17:51:36 +01:00 |
|
David Shah
|
ab063b2456
|
clangformat
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 18:37:17 +01:00 |
|
David Shah
|
11cdc197bc
|
ecp5: Fix global buffer connectivity and timing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 18:29:23 +01:00 |
|
David Shah
|
c5f9a12bb1
|
ecp5: Global router produces a working bitstream
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 17:36:08 +01:00 |
|
David Shah
|
2a0bb2be29
|
ecp5: Integrate global router and debug naming
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:49:29 +01:00 |
|
David Shah
|
97b12fa741
|
ecp5: Add DCC Bels, fix global router post-rebase
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:09:21 +01:00 |
|
David Shah
|
30f122854a
|
ecp5: Helper function and arch tweaks for global router
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:06:30 +01:00 |
|