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Author SHA1 Message Date
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
David Shah
7a2ef27d6c
Merge pull request #153 from YosysHQ/global-options 
ice40: Finer-grained control of global promotion
 2018-11-28 07:43:00 +00:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
David Shah
e99e2f1570
Merge pull request #152 from YosysHQ/compile_fix 
Fix compile on GCC 5.5 or older
 2018-11-27 18:32:24 +00:00
Miodrag Milanovic
0b5748a7af Fix compile on GCC 5.5 or older 2018-11-27 19:20:15 +01:00
David Shah
cdfd35e6aa
Merge pull request #150 from YosysHQ/err_warn_count 
Print warning and error count at end of execution
 2018-11-26 19:37:03 +00:00
David Shah
4a44bc569a Print warning and error count at end of execution 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 19:14:38 +00:00
David Shah
0adc0d7529 timing: Improve clock constraint log output 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 18:56:10 +00:00
David Shah
86108bfd39
Merge pull request #149 from smunaut/issue_148 
Fixes for global promotion
 2018-11-26 18:11:16 +00:00
David Shah
5a1190ade2 ecp5: Fix UR PLL tile coordinates 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 15:35:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit ! 
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
822b525035 placer1: During initial placement, don't rip-up strongly binded cells 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah
024db62ef0 Update README.md 
Fixes #74

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:47:16 +00:00
David Shah
fe670cf3f6 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:37:39 +00:00
David Shah
bbeab72ad9
Merge pull request #143 from daveshah1/ecp5_muxes 
ecp5: Adding support for LUT extension muxes up to LUT7
 2018-11-26 09:37:18 +00:00
David Shah
22ac41d627
Merge pull request #138 from YosysHQ/refactor_log 
Tidy up logging code, add log file support, make timing failures non-fatal errors
 2018-11-26 09:37:07 +00:00
David Shah
98858fe611
Merge pull request #139 from YosysHQ/fix_117 
router1: Fix unrouted, undriven nets
 2018-11-26 09:36:58 +00:00
David Shah
eda77a5244 json: Remove superfluous floating node message 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:36:43 +00:00
David Shah
fe2fa0e3ed ice40: Improve PCF error handling 
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:34:28 +00:00
David Shah
2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah
b035cb9fcf Add nonfatal error support and use for timing failures 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:22:42 +00:00
David Shah
ff978570b1
Merge pull request #146 from YosysHQ/fix_145 
ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
 2018-11-24 18:00:45 +00:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
David Shah
8bda861a71
Merge pull request #144 from bgamari/patch-1 
docs/constraints: Fix typo
 2018-11-22 21:56:30 +00:00
Ben Gamari
7a61ffc3f4
docs/constraints: Fix typo 2018-11-22 16:55:46 -05:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah
e48c9e73e7 python: Add wrapper for vectors to allow Python access to net.users 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 12:35:07 +00:00
David Shah
1731590160
Merge pull request #122 from YosysHQ/ecp5_timing 
ecp5: Use cell and pip timings from the Trellis database
 2018-11-22 11:55:25 +00:00
David Shah
48c793bd4d
Merge pull request #140 from xobs/readme-ubuntu-boost-list 
README: further specify required Boost packages for Ubuntu
 2018-11-22 08:52:30 +00:00
Sean Cross
bfbea5bcb7 README: further specify required Boost packages for Ubuntu 
UWhen installing Boost, you can either install libboost-all-dev, or install
just the required packages.

Previously, `libboost-dev` was the only required package listed.

This adds `libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev
libboost-python-dev` to the list of required packages.

It addresses issue #128.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-11-22 14:06:24 +08:00
David Shah
8471d4249c router1: Fix unrouted, undriven nets 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:23:20 +00:00
David Shah
15d05296db
Merge pull request #134 from YosysHQ/issue129 
QUIET flag for cmake searches for boost python
 2018-11-21 17:17:45 +00:00
David Shah
51d1363dfe Change the log level of some timing-related messages 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:13:53 +00:00
David Shah
b550791d92 Refactor log code and add log file support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:08:45 +00:00
David Shah
01377d3f87
Merge pull request #135 from smunaut/ice40_typo 
ice40/pll: Fix typo when testing for global port output net
 2018-11-21 16:30:51 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Eddie Hung
35b3aaf18f QUIET flag for cmake searches for boost python 2018-11-20 10:41:24 -08:00
Serge Bazanski
cf83d546f1
Merge pull request #133 from YosysHQ/yield_gui 
Add missing router1 ctx->yield() calls
 2018-11-20 19:31:29 +01:00
Clifford Wolf
b5d518583e Add missing router1 ctx->yield() calls 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 18:58:15 +01:00
David Shah
343569105d
Merge pull request #131 from smunaut/ice40_fixes 
iCE40: Bug fixes and general improvement of global network support
 2018-11-20 10:11:32 +00:00
David Shah
0fb7735e45
Merge pull request #130 from smunaut/issue_127 
common/placer1: In random pick, only use grid if there is more than 64 BELs
 2018-11-20 10:11:21 +00:00
David Shah
04c5ed45bb
Merge pull request #132 from maikmerten/master 
add "randomize-seed" command-line option
 2018-11-20 10:11:09 +00:00
Maik Merten
e167043e73 add "randomize-seed" command-line option 2018-11-19 19:45:12 +01:00
Sylvain Munaut
d6fd0e7e5b common/placer1: In random pick, only use grid if there is more than 64 BELs 
If you have a large grid and very few BELs of a given type, picking a
random grid location yields very little odds of finding a BEL of that
type.

So for those, just put all of them at (0,0) and do a true random pick.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:52:40 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00