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115 Commits

Author SHA1 Message Date
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Clifford Wolf
b4dc6b8845 Add info message for promoted global nets 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-03 13:40:21 +02:00
David Shah
7ef8a7415d ice40: Add error for bad PACKAGE_PIN connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-03 12:14:49 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf
07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf
1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah
f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah
2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
Miodrag Milanovic
f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Miodrag Milanovic
fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Sergiusz Bazanski
1bf22a7f64 ice40: make PLL packing more robust 2018-08-19 21:30:55 +01:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
fd2174149c Fixing constraint placement bugs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 16:29:44 +02:00
David Shah
7e9209878c Reworking packer and placer to use new generic rel legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:00:32 +02:00
David Shah
483f1b772c ice40: Promote 'logic' globals as well as clock/enable/reset 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:56:56 +02:00
David Shah
0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
Sergiusz Bazanski
85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung
950f33c1bb clangformat 2018-07-25 17:53:01 -07:00
Sergiusz Bazanski
db4f2d2318 ice40: check PLL PACKAGEPIN drives only PLL, cosmetics 2018-07-25 11:47:24 +01:00
Sergiusz Bazanski
c554ab1ef0 clang-format 2018-07-25 11:32:40 +01:00
Sergiusz Bazanski
aad0d3eb35 ice40: support PLL40_*_PAD, fix pass-through LUT for LOCK 2018-07-25 11:32:21 +01:00
Sergiusz Bazanski
2039112a47 ice40: after review 2018-07-24 15:59:18 +01:00
Sergiusz Bazanski
b31e95f82c Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll 2018-07-24 15:54:03 +01:00
David Shah
5a170f286c ice40: Remove use of deprecated APIs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 15:52:56 +02:00
David Shah
4359197dfe ice40: Trim BRAM constant inputs, reduces routing congestion around BRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:21:10 +02:00
Sergiusz Bazanski
90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
065ea95eab ice40: Move spliceLUT back to pack.cc 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
db31c0625b ice40: Fail early on SB_PLL40_*_PAD cells 2018-07-24 02:55:38 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
David Shah
79dc910b40 ice40: Trim DSP inputs that are constant where appropriate 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:32:30 +02:00
David Shah
bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah
08ceb8a059 ice40: Renaming 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:34:32 +02:00