Commit Graph

4668 Commits

Author SHA1 Message Date
Catherine
ebbaf8c08d common: disable parallel refinement only without threads.
Previously it was always disabled on WebAssembly builds.
2023-02-23 09:45:19 +01:00
Catherine
8f0731edc9 common: update deprecated use of boost::filesystem::basename. 2023-02-23 09:44:46 +01:00
Catherine
088c822e28 CMake: check if warning flag is supported before use.
Clang 11 is failing on -Wno-format-truncation.
2023-02-23 09:44:29 +01:00
Catherine
e94479ccd5
Merge pull request #1108 from whitequark/fix-includes
common: add missing includes for libc++
2023-02-23 04:13:10 +00:00
Catherine
4b4f4a7da1 common: add missing includes for libc++. 2023-02-23 02:32:19 +00:00
myrtle
0c4e0d4312
Merge pull request #1106 from YosysHQ/gatecat/fab_carry
fabulous: Add support for packing carry chains
2023-02-21 15:47:17 +01:00
gatecat
0ed964247e fabulous: Add support for packing carry chains
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-21 14:41:48 +01:00
myrtle
03b6fb3ddb
Merge pull request #1103 from rodgert/master
Include <cstdint> in common/kernel/hashlib.h
2023-02-21 11:50:43 +01:00
myrtle
19fec70aa3
Merge pull request #1105 from YosysHQ/gatecat/nexus-io-error
nexus: Check IO-bank compatibility
2023-02-21 11:50:34 +01:00
gatecat
61021a22ee nexus: Check IO-bank compatibility
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-21 11:18:35 +01:00
Thomas W Rodgers
825d646196 Include <cstdint> in common/kernel/hashlib.h
The definitions for uint32_t, uint64_t report as undefined when
compiling under GCC13. They were previously found by transitive
includes, but this is not guaranteed to work, and GCC13 forced
the issue.
2023-02-18 10:26:01 -08:00
gatecat
16bcc51ffb fabulous: Further tweak magic numbers
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-16 15:53:15 +01:00
myrtle
2275ff78e2
Merge pull request #1102 from rowanG077/print-random-seed
common: Print out generated seed value
2023-02-16 12:55:28 +01:00
myrtle
c65762b5c2
Merge pull request #1101 from YosysHQ/gatecat/fab-fake-timings
fabulous: Add fake timings
2023-02-16 12:18:00 +01:00
rowanG077
32e818204e common: Print out generated seed value 2023-02-16 12:02:00 +01:00
gatecat
06b675b345 fabulous: Add fake timings
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-16 11:56:58 +01:00
myrtle
78dabb7b8f
Merge pull request #1092 from rowanG077/werror
common: Implement Werror flag
2023-02-14 15:03:57 +01:00
Catherine
57693bcb7f
Update links to IceStorm in README
Fixes #1099.
2023-02-14 05:47:16 +00:00
myrtle
dd9426606a
Merge pull request #1098 from YosysHQ/lofty/fix-machxo2-pybindings
machxo2: Fix Python bindings for pip iterators
2023-02-13 14:07:51 +01:00
Lofty
52b02f7377 machxo2: Fix Python bindings for pip iterators 2023-02-13 12:49:00 +00:00
rowanG077
3608c3eb02 common: Implement Werror flag 2023-02-13 10:52:05 +01:00
myrtle
b5125aac31
Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ct
ecp5: Propagate clock constraints through DCSC
2023-02-13 10:25:07 +01:00
myrtle
ba3801e010
Merge pull request #1097 from YosysHQ/gatecat/fab-bram-fix
fabulous: Improve names for BRAM bels
2023-02-10 13:41:36 +01:00
gatecat
eb70e95079 fabulous: Improve names for BRAM bels
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-10 13:23:31 +01:00
myrtle
1226fad4f6
Merge pull request #1096 from YosysHQ/gatecat/ecp5-ioce-fix
ecp5: Handle the case where both CE are the same constant
2023-02-10 07:29:10 +01:00
gatecat
a8a88d4813 ecp5: Handle the case where both CE are the same constant
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-09 11:12:15 +01:00
myrtle
a93f49eb04
Merge pull request #1094 from uis246/master
gowin: Add bels for new types of oscillators
2023-02-07 09:20:59 +01:00
uis
69fe654f02 gowin: Add bels for new types of oscillator 2023-02-06 21:45:55 +00:00
rowanG077
9e8f8b7b45 streamline constant_net detection 2023-02-06 17:05:28 +01:00
rowanG077
d2bf44ba45 ecp5: DSCS clock propagation if modesel is 0 constant 2023-02-06 16:27:45 +01:00
myrtle
48b0025732
Merge pull request #1087 from yrabbit/gw1nr-9
gowin: Add PLL support for the GW1NR-9 chip
2023-02-02 08:30:56 +00:00
YRabbit
2edc77836d Merge branch 'master' into gw1nr-9 2023-02-02 07:35:38 +10:00
rowanG077
a38ee0786a ecp5: Propagate clock constraints through DSCS 2023-02-01 19:12:10 +01:00
myrtle
f328130c0a
Merge pull request #1089 from smunaut/icegate
ice40: Add support for PLL ICEGATE function
2023-02-01 14:34:29 +00:00
Sylvain Munaut
582410629b ice40: Don't assert on unknown extra_config bits if they are 0
Bits are 0 by default anyway, so if they are unknown (because icestorm
is too od) but we want them at 0 ... it's not much of an issue.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-02-01 15:14:18 +01:00
Sylvain Munaut
49ae495344 ice40: Add support for PLL ICEGATE function
Technically you can enable it independently on CORE and GLOBAL
output, but this is not exposed in the classic primitive, so
we do the same as icecube2 and enable/disable it for both output
path depending on the argument

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-02-01 11:41:35 +01:00
myrtle
235e0d28e9
Merge pull request #1088 from rowanG077/ecp5-singleton-lpf
ecp5: LOCATE in LPF works on singleton vector
2023-01-31 22:29:11 +00:00
rowanG077
803c57d052 ecp5: LOCATE in LPF works on singleton vector 2023-01-31 21:05:32 +01:00
YRabbit
5d5ea57e21 gowin: Add PLL support for the GW1NS-2C chip
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-31 18:46:38 +10:00
YRabbit
aac36ecf3f gowin: Add PLL support for GW1NR-4 chips
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-31 08:58:33 +10:00
myrtle
bfa3e047ce
Merge pull request #1086 from smunaut/out_z
ice40: Improve `output` handling vs pull-ups and undriven
2023-01-30 22:06:58 +00:00
YRabbit
2829a7d70a gowin: Proper use of the C++ mechanisms
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-30 18:59:09 +10:00
YRabbit
6a1212a1e1 gowin: Add PLL support for the GW1NR-9 chip
And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-30 12:49:57 +10:00
Sylvain Munaut
f50d4c1ed1 ice40: Support for undriven / unconnected output ports
If a port specified as output (and thus had a $nextpnr_obuf inserted)
is undriven (const `z` or const `x`), we make sure to not enable
the output driver. Also enable pull-ups if it was requested by the user.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-01-29 22:35:19 +01:00
Sylvain Munaut
0cf5006e3b ice40: Rework pull-up attribute copy to SB_IO blocks
We try to copy the attribute only when there is a chance for
the output driver to not be active.

Note that this can _also_ happen when a port is specified as
output but has a TBUF, which the previous code wasn't handling.

We could copy the attribute "all-the-time" but this would
mean if a user specified a `-pullup yes` in the PCF for a
permanently driven output pin, we'd be burning power for
nothing.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-01-29 22:35:19 +01:00
myrtle
f80b871dd5
Merge pull request #1084 from YosysHQ/gatecat/ecp5-ioff-fix
ecp5: Improve IOFF CE handling robustness
2023-01-27 11:20:45 +01:00
myrtle
d661d117af
Merge pull request #1085 from yrabbit/gw1nr-9c-pll
gowin: Add PLL support for the GW1NR-9C chip
2023-01-27 11:20:35 +01:00
YRabbit
2d45d57b32 gowin: Add PLL support for the GW1NR-9C chip
This chip is used in the Tangnano9k board.

  * all parameters of the rPLL primitive are supported;
  * all PLL outputs are treated as clock sources and optimized routing
    is applied to them;
  * primitive rPLL on different chips has a completely different
    structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
    as many as four, despite this unification was carried out and
    different chips are processed by the same functions, but this led to
    the fact that you can not use the PLL chip GW1N-1 with the old
    apicula bases - will issue a warning and refuse to encode primitive.
    In other cases compatibility is supported.
  * Cosmetic change: the usage report shows the rPLL names without any
    service bels.
  * I use ctx->idf() on occasion, it's not a total redesign.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-26 20:26:05 +10:00
gatecat
9b5e5f124c clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-25 10:29:32 +01:00
gatecat
c8cb063656 ecp5: Improve IOFF CE handling robustness
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-25 09:26:12 +01:00