Clifford Wolf
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ac67482380
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Remove pool, dict, vector namespace aliases
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-11 19:56:33 +02:00 |
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Clifford Wolf
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f63eec034f
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Add conflicting=false argument to bind getters
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-11 19:46:03 +02:00 |
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Miodrag Milanovic
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d8d38cd107
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Draw fpga model
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2018-06-10 19:56:17 +02:00 |
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Miodrag Milanovic
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67227847e5
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Pass design to gui, display chip name
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2018-06-10 18:25:23 +02:00 |
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Clifford Wolf
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0bc5b1c2d9
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Add dummy implementations of dummy Chip API
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-09 18:31:35 +02:00 |
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David Shah
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7f330af9f3
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Reformat remaining files
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-06-08 11:04:02 +02:00 |
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Clifford Wolf
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37d2fc65b1
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Fix placer build for dummy arch
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-07 17:50:36 +02:00 |
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Clifford Wolf
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1ea8fa4881
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clang-format for design and chip codebase
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-07 12:56:49 +02:00 |
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Clifford Wolf
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9afa6a2016
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Update and simplify dummy arch
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-06-06 15:30:23 +02:00 |
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Clifford Wolf
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1338f0f9eb
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Add Makefile
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-05-26 11:17:50 +02:00 |
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Clifford Wolf
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5e48758b30
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Directory structure
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-05-26 10:47:35 +02:00 |
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