Commit Graph

106 Commits

Author SHA1 Message Date
Keith Rothman
ae71206e1f Update FPGA interchange chipdb to v4 with inverter data.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:01:45 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:01:43 -07:00
Keith Rothman
af1fba9f52 Update latest version of FPGA interchange schema.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:00:58 -07:00
Keith Rothman
8d1eb0a195 Initial lookahead for FPGA interchange.
Currently the lookahead is disabled by default because of the time to
compute and RAM usage.  However it does appear to work reasonably well
in testing.  Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 08:16:50 -07:00
gatecat
9ef412c2cc
Merge pull request #638 from litghost/fixup_physical_netlist_writer
Correct some bugs in writing of physical netlist w.r.t. site sources.
2021-03-22 18:32:26 +00:00
gatecat
a3ed97c0db
Merge pull request #637 from litghost/refine_site_router
Refine site router
2021-03-22 18:32:04 +00:00
gatecat
e8d36bf5bd
Merge pull request #634 from litghost/add_get_bel_pin_type
Add getBelPinType to Python interface.
2021-03-22 18:31:48 +00:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router.
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:54:49 -07:00
Keith Rothman
0f4014615c Add missing dependencies to CMake targets.
- Add additional targets useful for various situations.
 - Have counter test use common remap.v file.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:47:33 -07:00
Keith Rothman
06bcde6243 Correct some bugs in writing of physical netlist w.r.t. site sources.
Local site sources should have their driving BEL pin included in the net
so that the site wire is driven by an output BEL pin.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:46:43 -07:00
Keith Rothman
4cd74bba2c Add getBelPinType to Python interface.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:25:45 -07:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API.
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:17:55 -07:00
Keith Rothman
db12a83ced Add pseudo pip data to chipdb (with schema bump).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:33:12 +00:00
Keith Rothman
2cd5bacca0 Refactor header structures in FPGA interchange Arch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-19 21:36:06 -07:00
Keith Rothman
f4dc67879e Fixup GUI link dependencies on headers from libraries.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-18 14:00:19 -07:00
Alessandro Comodi
01a95faf21 fpga_interchange: temporarily disable failing test
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-17 10:32:35 +01:00
Alessandro Comodi
f6583f7ecc fpga_interchange: minor fixes and comments addition
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 22:59:20 +01:00
Alessandro Comodi
c1e668f823 fpga_interchange: address review comments
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 22:02:06 +01:00
Alessandro Comodi
f9e9fadbc8 github-actions: use capnp v0.8.0
This also updates the note in the README for the FPGA interchange

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 16:57:07 +01:00
Alessandro Comodi
f63a9a48a4 fpga_interchange: re-add README with updated instructions
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
f52b5b39ed fpga_interchange: tests: add techmap optional source file
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
3f3cabea2d fpga_interchange: add bbasm step and archcheck
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
0b62e540a3 fpga_interchange: address review comments
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
bd2da27e4e fpga_interchange: tests: added comment and fixed XDC
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
e5cc03965e fpga_interchange: chipdb: use generic patching function
Also moved the RapidWright invocation script path under a CMake variable

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:02 +01:00
Alessandro Comodi
490fdb0a1c fpga_interchange: cmake: generate only one device family
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:01 +01:00
Alessandro Comodi
77ffdd7fd4 fpga_interchange: tests: add cmake functions
Also move all tests in a tests directory

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:01 +01:00
Alessandro Comodi
d77d0ff34a fpga_intrchange: add cmake infrastructure to generate chipdbs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-16 15:39:01 +01:00
Keith Rothman
351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 18:49:12 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
fba71bd182 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-03 10:39:47 +00:00
Keith Rothman
71b92cb813 Update FPGA interchange README.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
78748a67be For now just return false in the site router.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
9cbfd0b967 Add counter test.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange.
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
184665652e Finish dedicated interconnect implementation.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
5574455d2a Working FF example now that constant merging is done.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
cd8297f54d Move RapidWright git URI back to upstream.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
5c6e231412 Remove some signedness warnings.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
46b38f8a40 Fix reference copy.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
3ccb164f2a Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
15459cae91 Initial working constant network support!
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
cf554f9338 Add constant network test case.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
3e5a23ed5b Add tests to confirm constant routing import.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
761d9d9229 Correct some bugs in the create_bba Makefile.
Also add debug_test target to debug archcheck.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
40df4f4f65 Add initial constant network support to FPGA interchange arch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:08:54 -08:00