4 Commits

Author	SHA1	Message	Date
YRabbit	ae89430075	gowin: add global VCC and VSS networks ... - VSS and VCC sources in each cell are used; - constant LUT inputs are disabled; - putting the class declaration into a header file. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2023-08-31 08:28:09 +02:00
YRabbit	fb5f764b85	gowin: Add himbaechel arch ... - wires, nodes and whites are generated from bases - apicula; - roting of SN and EW bidirectional wires is supported; - supports "wrapping" the wires at the edges of the chip; - LUT1-4 and two types of DFF(R) are supported; - simple IO is supported. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2023-08-31 08:28:09 +02:00
YRabbit	24e1734999	generate bba ... Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2023-08-31 08:28:09 +02:00
YRabbit	bc7cd4f20e	wip start	2023-08-31 08:28:09 +02:00