Commit Graph

702 Commits

Author SHA1 Message Date
Sylvain Munaut
b274a8f8f0 ice40/pack: Copy attributes to packed RAM cells
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-01-19 15:49:21 +01:00
David Shah
7d8b729ff4 ice40: Add timing data for all IO modes
Signed-off-by: David Shah <dave@ds0.me>
2019-01-07 17:18:40 +00:00
David Shah
4444a39fd4 ice40: Improve handling of unconstrained IO
Signed-off-by: David Shah <dave@ds0.me>
2018-12-26 16:00:19 +00:00
David Shah
953a3ac552 ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn
Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-20 20:52:54 +00:00
David Shah
75335d4e1a ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs
Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-20 18:50:34 +00:00
David Shah
51155ec6a7 ci: Add attosoc smoketest for ice40
Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-08 17:09:27 +00:00
David Shah
d790d0bb91
Merge pull request #163 from daveshah1/timing_opt
Adding criticality calculation and experimental timing optimisation pass
2018-12-07 21:19:41 +00:00
David Shah
144363693d ice40: Report error for unsupported PLL FEEDBACK_PATH values
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:29:33 +00:00
David Shah
e7fc42ac84 ice40: Improve bitstream error handling
Fixes #161 and provides a clearer error for #170

Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:19:48 +00:00
David Shah
b732e42fa3 timing_opt: Reduce iterations to 30, tidy up logging
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:00:16 +00:00
David Shah
f53dc8d3c9 timing_opt: Improve heuristics
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
David Shah
f3adf5a576 timing_opt: Make an optional pass controlled by command line
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
David Shah
254c5ea359 clangformat
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
David Shah
b51308708b timing_opt: Debugging and integration
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
David Shah
88e1e6bdf4 clangformat
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:52:46 +00:00
David Shah
dbaabae235 ice40: Put debug logging behind ctx->debug
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:51:17 +00:00
David Shah
d298687dc2 ice40: Fix carry chain splitting
Signed-off-by: David Shah <dave@ds0.me>
2018-12-05 10:12:23 +00:00
David Shah
51cda136b1 ice40: Don't split carry chain in simple feed-out cases
Signed-off-by: David Shah <dave@ds0.me>
2018-12-04 12:31:32 +00:00
David Shah
0c93b55650 ice40: Include I3 connectivity in chain
Thanks @smunaut

Signed-off-by: David Shah <dave@ds0.me>
2018-12-04 12:02:26 +00:00
whitequark
7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block.
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
2018-12-01 22:27:04 -03:00
David Shah
8af367ad0a ice40: Add a warning for unconstrained IO
Signed-off-by: David Shah <dave@ds0.me>
2018-11-29 19:35:19 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types
Signed-off-by: David Shah <dave@ds0.me>
2018-11-29 19:26:23 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh
ice40: raise CE global promotion threshold
2018-11-29 09:12:47 +00:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
David Shah
0872b63b0b
Merge pull request #155 from smunaut/issue_151
ice40: Update the way LVDS inputs are handled during bitstream generation
2018-11-28 16:20:36 +00:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:43 +01:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:23 +01:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion
Signed-off-by: David Shah <dave@ds0.me>
2018-11-27 19:06:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit !
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
David Shah
fe2fa0e3ed ice40: Improve PCF error handling
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
2018-11-26 09:34:28 +00:00
David Shah
2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
Signed-off-by: David Shah <dave@ds0.me>
2018-11-24 17:49:26 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working
Signed-off-by: David Shah <dave@ds0.me>
2018-11-22 13:42:20 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
325d46e284 ice40/chipdb: Add wires to global network for all cells that can drive it
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
c219d8fe4d ice40: Fix BEL validity check for PLL vs SB_IO
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
9483a95a4a ice40: Improve the is_sb_pll40_XXX predicates collection
- Add a test for dual output PLL variant
 - Make them handle the packet version of the cell

 This will become useful for various tests during PLL rework

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
f6d6022984 ice40: Fix PLLTYPE for SB_PLL40_2F_PAD
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00