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Author SHA1 Message Date
gatecat
b2e9ce46f1
Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaks 
nexus: Tweaks for router1 performance
 2021-09-22 22:04:56 +01:00
gatecat
41c07126ec
Merge pull request #821 from YosysHQ/gatecat/dsp-fix 
nexus: Fix DSP macro placement
 2021-09-22 16:57:49 +01:00
gatecat
fed682ee5f nexus: Tweaks for router1 performance 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 14:55:10 +01:00
gatecat
4d90850676 placer1: Remove redundant relative constraint check 
Macros with potentially inconsistent spacing are now permissible.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 13:14:45 +01:00
gatecat
53e94653f3 nexus: Fix DSP macro placement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 13:12:21 +01:00
gatecat
035452d938
Merge pull request #815 from antmicro/nexus-fix-siologic-handling 
nexus: Fixed an improved SIOLOGIC handling
 2021-09-20 13:15:39 +01:00
Maciej Kurc
80e2f8a791 Added support for syn_useioff for enabling tri-state control FF integration into IOLOGIC. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:35:36 +02:00
gatecat
e926cddca2 placer1: Fix cluster swap cost updates 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 11:11:24 +01:00
gatecat
4730a4f339 timing: Always use max delay for required time 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 11:04:39 +01:00
gatecat
287a860283 timing: Fix slack for unconstrained clocks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 10:43:19 +01:00
gatecat
d17b5faf76
Merge pull request #817 from YosysHQ/gatecat/chain-swap 
placer1: Allow swapping chains with other chains
 2021-09-18 09:25:32 +01:00
gatecat
f119f56e63 placer1: Allow swapping chains with other chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-17 21:51:18 +01:00
Maciej Kurc
8ffd30cb2d Use correct names for IDDRX1_ODDRX1 FASM features 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 15:52:56 +02:00
Maciej Kurc
ef9eee6b15 Added automatic inference and integration of FFs driving T pin into IOLOGIC 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
Maciej Kurc
6948d41616 Added handling of the case when tri-state control net bypasses SIOLOGIC bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
gatecat
7c82a04df5
Merge pull request #813 from YosysHQ/gatecat/py-on-fail 
command: Allow running Python on failure for state introspection
 2021-09-17 09:29:38 +01:00
gatecat
1e4f706ace command: Allow running Python on failure for state introspection 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-16 20:56:32 +01:00
gatecat
67bd349e8f
Merge pull request #806 from yrabbit/extend-placement 
gowin: Add constraints on primitive placement.
 2021-09-08 19:01:34 +01:00
gatecat
95845b47b5
Merge pull request #808 from acomodi/fix-xdc 
interchange: xdc: add more not_implemented commands
 2021-09-08 15:56:41 +01:00
Alessandro Comodi
258b46125f interchange: xdc: add more not_implemented commands 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-08 15:15:58 +02:00
YRabbit
544d6073bc Merge branch 'master' into extend-placement 2021-09-08 09:31:42 +10:00
gatecat
675a96fc5a
Merge pull request #807 from acomodi/fix-xdc 
interchange: xdc: add common not_implemented function
 2021-09-07 17:01:37 +01:00
Alessandro Comodi
46fc902bcf interchange: xdc: add common not_implemented function 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-07 16:47:37 +02:00
YRabbit
9368671ca9 Merge branch 'master' into extend-placement 2021-09-07 09:18:28 +10:00
gatecat
d4a14a0d04 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-06 13:29:52 +01:00
gatecat
d08fb255a2 router2: Fix uninitialised values 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-06 13:29:23 +01:00
YRabbit
d6fdd6c7ce Merge branch 'combine-dff' into extend-placement 2021-09-04 17:39:09 +10:00
YRabbit
e4701f2da1 Merge branch 'master' into extend-placement 2021-09-04 16:29:21 +10:00
gatecat
fd6366f027 nexus: Fix getBelGlobalBuf 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:23:11 +01:00
gatecat
01b51fb715 router2: Fix explored count 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:08:54 +01:00
YRabbit
e82d49e13a Merge branch 'master' into combine-dff 2021-09-02 18:19:30 +10:00
gatecat
0c40bed425
Merge pull request #790 from acomodi/place-only-same-cluster-in-site 
interchange: place only cells belonging to the same clusters in the same site
 2021-08-31 12:37:04 +01:00
Alessandro Comodi
e0950408d5 interchange: clusters: fix other cluster allowance checks in same site 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:44:36 +02:00
Alessandro Comodi
2df931f7db interchange: entirely disable cache when binding site routing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:08:46 +02:00
Alessandro Comodi
85cf6562b6 gh: interchange: bump python-interchange tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 11:54:22 +02:00
YRabbit
f3899696a7 gowin: Place DFFs of different types in the slice. 
Allow the registers of the same type or pairs shown below to be
placed in the same slide:

|--------|--------|
| DFFS   | DFFR   |
| DFFSE  | DFFRE  |
| DFFP   | DFFC   |
| DFFPE  | DFFCE  |
| DFFNS  | DFFNR  |
| DFFNSE | DFFNRE |
| DFFNP  | DFFNC  |
| DFFNPE | DFFNCE |

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-31 07:53:15 +10:00
YRabbit
23a5e91858 gowin: Add constraints on primitive placement. 
Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-31 07:36:11 +10:00
Alessandro Comodi
78bf5796db interchange: disallow placing cells on sites with clusters 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-27 13:47:10 +02:00
gatecat
0e83db47a0 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 14:58:43 +01:00
gatecat
7f8e467acd
Merge pull request #805 from YosysHQ/gatecat/py-portref-byvalue 
python: Wrap PortRef by value
 2021-08-26 14:57:46 +01:00
gatecat
b85fe12234 python: Wrap PortRef by value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 13:23:16 +01:00
gatecat
6fc41692d6
Merge pull request #710 from Ravenslofty/mistral-mlab-as-lab 
mistral: Use MLABs as if they're LABs (for now)
 2021-08-24 18:25:44 +01:00
gatecat
0367719eea mistral: Permute MLAB init bits correctly 2021-08-24 15:39:45 +01:00
gatecat
e15f0db408 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-24 12:48:08 +01:00
gatecat
86393c8c8e
Merge pull request #801 from yrabbit/TRBL-style 
gowin: Add the IO[TRBL]style placement recognition
 2021-08-23 21:58:08 +01:00
gatecat
42166f2e3e
Merge pull request #802 from YosysHQ/gatecat/python-rt-dly 
python: Allow querying route delays
 2021-08-23 21:56:42 +01:00
gatecat
de311e052f python: Allow querying route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-23 20:51:53 +01:00
YRabbit
e4196f32d3 gowin: Add the IO[TRBL]style placement recognition 
Specifying pin placement with this notation (e.g. IOR4B) allows
to use the same constraint file without changes for different
packages and even different families.
The vendor router also understands this notation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-23 16:19:02 +10:00
gatecat
897a2fccb6
Merge pull request #798 from kleinai/extref-loc 
Make EXTREFB handling more robust
 2021-08-19 16:36:18 +01:00
gatecat
6ae9b47155
Merge pull request #800 from smunaut/fix_py_portrefvector 
pybindings: Fix mapping for PortRefVector
 2021-08-19 12:36:32 +01:00