David Shah
|
c5a3571a06
|
ecp5: Working on DCU
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
983903887d
|
ecp5: DCU bitstream gen handling
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
cc9fb1497d
|
ecp5: Groundwork for DCU support
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
Eddie Hung
|
2d39cde17b
|
Merge remote-tracking branch 'origin/master' into timingapi
|
2018-11-13 12:12:11 -08:00 |
|
Eddie Hung
|
3b2b15dc4a
|
Merge pull request #107 from YosysHQ/router_improve
Major rewrite of "router1"
|
2018-11-13 11:39:51 -08:00 |
|
David Shah
|
959d163ba7
|
ecp5: Improve delay estimates
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-13 14:27:23 +00:00 |
|
Pedro Vanzella
|
710ea1b265
|
Mark getArchOptions as override in derived classes
|
2018-11-13 11:03:48 -02:00 |
|
Clifford Wolf
|
06e0e1ffee
|
Various router1 fixes, Add BelId/WireId/PipId::operator<()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-13 05:05:56 +01:00 |
|
David Shah
|
d3ad522bfe
|
ecp5: Copy clock constraints during global promotion
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
fc5e6bec9a
|
timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
11579a1046
|
ecp5: EBR clocking fix
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
8af86ff37d
|
ecp5: Update arch to new timing API
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
Clifford Wolf
|
6002a0a80a
|
clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 19:48:15 +01:00 |
|
Clifford Wolf
|
f93129634b
|
Add getConflictingWireWire() arch API, streamline getConflictingXY semantic
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 17:28:41 +01:00 |
|
David Shah
|
9e5aded5c6
|
ecp5: Fix 85k PLL_LR
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-11 15:12:27 +00:00 |
|
Clifford Wolf
|
d2bdb670c0
|
Add getConflictingPipWire() arch API, router1 improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 11:34:38 +01:00 |
|
Miodrag Milanovic
|
0ad5197ff4
|
show 4th tresllis_io in tile bounds
|
2018-11-11 08:25:54 +01:00 |
|
William D. Jones
|
14ad19e064
|
Use native PATH environment-variable separator on Windows for PYTHONPATH. Fixes 'Bad address' error in cmake.
Signed-off-by: William D. Jones <thor0505@comcast.net>
|
2018-11-03 13:12:37 -04:00 |
|
William D. Jones
|
553c611936
|
Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided io.h.
Signed-off-by: William D. Jones <thor0505@comcast.net>
|
2018-11-03 13:11:01 -04:00 |
|
David Shah
|
04f9b87101
|
ecp5: Allow setting IO SLEWRATE
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-01 20:41:51 +00:00 |
|
David Shah
|
e005cc6754
|
ecp5: Add PLL support
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 19:52:41 +00:00 |
|
David Shah
|
24a2feda30
|
ecp5: Separate global promotion and routing
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 16:22:34 +00:00 |
|
David Shah
|
c782f07b1b
|
ecp5: Add IO buffer insertion
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 11:30:09 +00:00 |
|
David Shah
|
db0646be8a
|
ecp5: Adding LPF parser
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 10:48:54 +00:00 |
|
David Shah
|
0ac48c6a08
|
ecp5: DSP fixes
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-22 16:18:29 +01:00 |
|
David Shah
|
535a6f625a
|
ecp5: Working on DSPs
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-22 11:19:59 +01:00 |
|
David Shah
|
1a06f4b2bd
|
ecp5: Adding DSP support
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 20:07:18 +01:00 |
|
David Shah
|
b5faa7ad10
|
ecp5: Implement ECP5 equivalent of c9059fc
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 17:15:34 +01:00 |
|
David Shah
|
1cde208090
|
clangformat
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:58 +01:00 |
|
David Shah
|
8aac6db44b
|
ecp5: Add support for correct tile naming in all variants
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:24 +01:00 |
|
David Shah
|
3aa3f5d796
|
ecp5: Add DP16KD timing analysis
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 13:30:23 +01:00 |
|
David Shah
|
1fc2318c53
|
ecp5: Optimise DCC placement
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-14 13:22:47 +01:00 |
|
David Shah
|
bda94aa5a5
|
ecp5: Fix BRAM tile names
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-11 11:51:17 +01:00 |
|
David Shah
|
848ce6d41c
|
ecp5: Fixing BRAM initialisation
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-10 17:21:37 +01:00 |
|
David Shah
|
f7466110a5
|
ecp5: Working on BRAM initialisation
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-09 13:13:16 +01:00 |
|
David Shah
|
d716292e3d
|
ecp5: BRAM improvements with constant/inverted inputs
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-06 15:59:22 +01:00 |
|
David Shah
|
cd688a2784
|
ecp5: Fixing EBR constant tie-offs
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 16:47:03 +01:00 |
|
David Shah
|
85a95ec250
|
ecp5: Bitstream gen for DP16KD BRAM
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 15:53:41 +01:00 |
|
David Shah
|
56ab547aeb
|
ecp5: Infrastructure for BRAM bitstream gen
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 14:36:16 +01:00 |
|
David Shah
|
19f828c91c
|
ecp5: Dummy timing entry for BRAM
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 11:35:37 +01:00 |
|
David Shah
|
48f08e6d39
|
ecp5: Adding constids for blockram
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 10:54:30 +01:00 |
|
David Shah
|
bf7161d2b4
|
ecp5: Negative clock support, general slice improvements
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-02 15:50:45 +01:00 |
|
David Shah
|
8cbc92b7f3
|
ecp5: Small DRAM routing fixes
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 18:45:14 +01:00 |
|
David Shah
|
9ebec3b87f
|
clangformat
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 18:20:14 +01:00 |
|
David Shah
|
fd4498736e
|
ecp5: Fix packing of FFs into carry/DRAM slices
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 18:19:56 +01:00 |
|
David Shah
|
2c96d4770d
|
ecp5: Fix DRAM initialisation
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 18:15:11 +01:00 |
|
David Shah
|
3dfc5b864a
|
ecp5: Remove broken DRAM timing arc
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 17:51:36 +01:00 |
|
David Shah
|
c8a9bb807c
|
ecp5: Debugging DRAM packing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 17:45:35 +01:00 |
|
David Shah
|
9518c5d762
|
ecp5: Working on DRAM packing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 17:05:02 +01:00 |
|
David Shah
|
885fae8236
|
ecp5: Handling of DRAM initialisation and wiring
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 16:43:22 +01:00 |
|
David Shah
|
d770eb672f
|
ecp5: Helper functions for distributed RAM support
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 15:23:12 +01:00 |
|
David Shah
|
931c78b1bb
|
ecp5: Improve handling of constant CCU2C inputs
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-01 14:42:19 +01:00 |
|
David Shah
|
e7c8818424
|
ecp5: Fix carry feed out
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 19:27:06 +01:00 |
|
David Shah
|
6a1b49c311
|
ecp5: Improve mixed no-FF/FF placement
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 18:39:53 +01:00 |
|
David Shah
|
3e399c9f20
|
ecp5: Carry packing fixes
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 18:10:20 +01:00 |
|
David Shah
|
9218d2e56b
|
ecp5: Relative placement and bitstream gen for carries
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 17:42:47 +01:00 |
|
David Shah
|
fef29d8762
|
ecp5: First stages of carry packing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 17:18:30 +01:00 |
|
David Shah
|
e81a95cf7e
|
ecp5: Add ccu2c_to_slice
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 17:06:06 +01:00 |
|
David Shah
|
2628344298
|
ecp5: Support code for carry chain handling
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 16:58:02 +01:00 |
|
David Shah
|
a27c7b45de
|
Refactor chain finder to its own file
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 16:29:26 +01:00 |
|
David Shah
|
6afc2c75fd
|
ecp5: Adding carry helper functions
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-30 15:13:31 +01:00 |
|
David Shah
|
0e0ad26f07
|
ecp5: Use ArchNetInfo to mark global nets to ignore
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 19:31:49 +01:00 |
|
David Shah
|
ab063b2456
|
clangformat
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 18:37:17 +01:00 |
|
David Shah
|
11cdc197bc
|
ecp5: Fix global buffer connectivity and timing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 18:29:23 +01:00 |
|
David Shah
|
f46f205782
|
ecp5: Fix handling of global to fabric connections
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 18:06:08 +01:00 |
|
David Shah
|
5e46d1eb98
|
ecp5: Remove excessive debugging from global promoter
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 17:38:39 +01:00 |
|
David Shah
|
c5f9a12bb1
|
ecp5: Global router produces a working bitstream
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 17:36:08 +01:00 |
|
David Shah
|
c2a062d254
|
ecp5: Fixing global to global user routing
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 17:13:50 +01:00 |
|
David Shah
|
9ff5d5a735
|
ecp5: Fixing global router bugs
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 17:01:19 +01:00 |
|
David Shah
|
2a0bb2be29
|
ecp5: Integrate global router and debug naming
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:49:29 +01:00 |
|
David Shah
|
4cd582478b
|
ecp5: Adding main global promoter/router function
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:37:18 +01:00 |
|
David Shah
|
f7a270a1d8
|
ecp5: Fix globals.cc following API update
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:15:17 +01:00 |
|
David Shah
|
c8674652dc
|
ecp5: Add SPINE routing to global router
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:09:21 +01:00 |
|
David Shah
|
24414614d2
|
ecp5: Import SPINE data to database
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:09:21 +01:00 |
|
David Shah
|
dfdaaa6f57
|
ecp5: Adding DCCA insertion function
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:09:21 +01:00 |
|
David Shah
|
97b12fa741
|
ecp5: Add DCC Bels, fix global router post-rebase
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:09:21 +01:00 |
|
David Shah
|
bc10a5646d
|
ecp5: Working on global router
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:06:30 +01:00 |
|
David Shah
|
d43138b022
|
ecp5: Global routing algorithm up to TAPs
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:06:30 +01:00 |
|
David Shah
|
7d48acff52
|
ecp5: Clock usage counter function
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:06:30 +01:00 |
|
David Shah
|
30f122854a
|
ecp5: Helper function and arch tweaks for global router
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-09-29 16:06:30 +01:00 |
|
David Shah
|
39e79db854
|
ecp5: clangformat
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-19 17:12:03 +01:00 |
|
David Shah
|
1b3a201a54
|
ecp5: Fix delay heuristic
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-19 17:10:55 +01:00 |
|
David Shah
|
ec94848774
|
ecp5: Add cell delays
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-19 16:59:36 +01:00 |
|
David Shah
|
cdc9dc545e
|
ecp5: Add crude approximation of Pip delays
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-19 14:29:16 +01:00 |
|
David Shah
|
45bd0a8c72
|
Merge pull request #54 from daveshah1/ecp5_speedup
ecp5: Improving placement speed
|
2018-08-19 14:04:01 +01:00 |
|
David Shah
|
0b35cb4e60
|
ecp5: Flatten bel_to_cell for performance
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-18 19:04:32 +01:00 |
|
David Shah
|
72a9a475fa
|
ecp5: Speed up Bel availability/binding checks
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-18 18:36:13 +01:00 |
|
Clifford Wolf
|
26be6f9761
|
Merge pull request #47 from YosysHQ/settings_propagate
Use settings for placer1 and router1
|
2018-08-18 19:25:19 +02:00 |
|
David Shah
|
b8206d71ca
|
ecp5: Speedup placement using ArchCellInfo
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-18 18:14:18 +01:00 |
|
Clifford Wolf
|
97520bb728
|
Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr
|
2018-08-18 13:06:21 +02:00 |
|
David Shah
|
5fe29922fd
|
ecp5: Speedup router with slightly better estimates
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-18 11:54:53 +02:00 |
|
Clifford Wolf
|
428f0b9eba
|
Add Arch attrs API
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-08-14 17:16:14 +02:00 |
|
Miodrag Milanovic
|
93a0d24560
|
Use settings for placer1 and router1
|
2018-08-09 18:39:10 +02:00 |
|
David Shah
|
ed602baa06
|
Merge pull request #42 from YosysHQ/floorplan
Add basic data structures for floorplanning
|
2018-08-09 10:49:11 +02:00 |
|
David Shah
|
834f7e4bfd
|
ecp5: Implement getPipLocation and related API
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-09 10:39:53 +02:00 |
|
Miodrag Milanovic
|
61bce47f3c
|
Use settings for json and pcf
|
2018-08-08 20:14:18 +02:00 |
|
Clifford Wolf
|
f6189e4677
|
Merge branch 'master' of github.com:YosysHQ/nextpnr into constids
|
2018-08-08 19:35:13 +02:00 |
|
David Shah
|
cd4e761bb7
|
Merge pull request #44 from YosysHQ/improve_timing_spec
Speed up budget allocator using topographical ordering and update cell timing API
|
2018-08-08 19:23:47 +02:00 |
|
David Shah
|
a3ae3f9791
|
ecp5: Update to use const IdStrings in place of PortPin/BelType
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-08-08 19:08:43 +02:00 |
|
Miodrag Milanovic
|
fc5cee6fb8
|
clangformat
|
2018-08-08 18:17:34 +02:00 |
|