gatecat
9b51c6e337
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-30 14:51:33 +02:00
Rowan Goemans
5488cd994b
router: Enable clock skew analysis during routing
2024-09-24 08:57:21 +02:00
gatecat
4a4025192a
run clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-12-26 09:54:34 +01:00
gatecat
4c6003ac0b
router2: Don't use estimates for constant nets
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-11-07 15:55:22 +01:00
gatecat
fe52840054
archapi: Add new API for global constant routing
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-11-07 09:00:03 +01:00
rowanG077
e8602fb56d
std::numeric_limits<delay_t>::lowest() -> ::min()
2023-09-28 16:27:15 +02:00
gatecat
e08471dfaf
router2: Improve robustness when critical nets conflict
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-08-24 09:20:44 +02:00
gatecat
54b2045726
clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2023-06-20 10:58:18 +02:00
rowanG077
914999673c
Rip out budgets
2023-06-20 10:57:10 +02:00
Lofty
cbd6496d35
router2: fix 8935c186 (again)
2023-06-19 13:47:23 +02:00
Lofty
787fac7649
router2: fix 8935c186
2023-06-14 03:40:48 +01:00
Lofty
71a6b99633
router2: revisit nodes with lower delay
2023-06-13 08:24:01 +01:00
Lofty
8935c1867f
router2: revisit nodes with lower cost
2023-06-13 08:24:01 +01:00
Lofty
5936464967
router2: add alternate weight option ( #1162 )
2023-05-25 10:47:10 +02:00
gatecat
132a98a91d
router1: Add error when dest port has no wire
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-06 14:15:48 +01:00
gatecat
7845b66512
Add missing <set> includes
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-20 09:04:41 +01:00
gatecat
e260ac33ab
refactor: ArcBounds -> BoundingBox
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:00:53 +01:00
gatecat
415c097df8
router2: Reserve source wire, too
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-09-20 13:42:51 +02:00
Miodrag Milanovic
1aa797b820
Fix parameter order
2022-08-22 12:32:50 +02:00
gatecat
09e388f453
netlist: Add PseudoCell API
...
When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.
The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
2022-07-08 14:30:57 +02:00
gatecat
49f178ed94
Split up common into kernel,place,route
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-08 13:42:54 +01:00
