This chip is used in the Tangnano9k board.
* all parameters of the rPLL primitive are supported;
* all PLL outputs are treated as clock sources and optimized routing
is applied to them;
* primitive rPLL on different chips has a completely different
structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
as many as four, despite this unification was carried out and
different chips are processed by the same functions, but this led to
the fact that you can not use the PLL chip GW1N-1 with the old
apicula bases - will issue a warning and refuse to encode primitive.
In other cases compatibility is supported.
* Cosmetic change: the usage report shows the rPLL names without any
service bels.
* I use ctx->idf() on occasion, it's not a total redesign.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* both instances of the new PLLVR type are supported;
* primitive placement is optimized for the use of dedicated PLL clock
pins;
* all 4 outputs of each primitive can use the clock nets (only 5 lines
in total at the same time so far).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.
Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.
Fully compatible with older versions of Apicula.
Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Both the mode used by yosys and all Gowin primitive modes are supported.
- The ALU always starts with a zero slice.
- The maximum length of the ALU chain is limited to one line of the chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
