Bits are 0 by default anyway, so if they are unknown (because icestorm
is too od) but we want them at 0 ... it's not much of an issue.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Technically you can enable it independently on CORE and GLOBAL
output, but this is not exposed in the classic primitive, so
we do the same as icecube2 and enable/disable it for both output
path depending on the argument
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If a port specified as output (and thus had a $nextpnr_obuf inserted)
is undriven (const `z` or const `x`), we make sure to not enable
the output driver. Also enable pull-ups if it was requested by the user.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
We try to copy the attribute only when there is a chance for
the output driver to not be active.
Note that this can _also_ happen when a port is specified as
output but has a TBUF, which the previous code wasn't handling.
We could copy the attribute "all-the-time" but this would
mean if a user specified a `-pullup yes` in the PCF for a
permanently driven output pin, we'd be burning power for
nothing.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This chip is used in the Tangnano9k board.
* all parameters of the rPLL primitive are supported;
* all PLL outputs are treated as clock sources and optimized routing
is applied to them;
* primitive rPLL on different chips has a completely different
structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
as many as four, despite this unification was carried out and
different chips are processed by the same functions, but this led to
the fact that you can not use the PLL chip GW1N-1 with the old
apicula bases - will issue a warning and refuse to encode primitive.
In other cases compatibility is supported.
* Cosmetic change: the usage report shows the rPLL names without any
service bels.
* I use ctx->idf() on occasion, it's not a total redesign.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Eigen considers the EIGEN3_INCLUDE_DIRS and EIGEN3_DEFINITIONS variables
to be deprecated and they will no longer be exported in the next release
after 3.4.0:
f2984cd077
Use the IMPORTED target instead, which seems to be the preferred way of
consuming third-party CMake libraries.
The chip used in tangnano4k does not have such pins, but we call the
function anyway in the expectation of other chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* both instances of the new PLLVR type are supported;
* primitive placement is optimized for the use of dedicated PLL clock
pins;
* all 4 outputs of each primitive can use the clock nets (only 5 lines
in total at the same time so far).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Each DSP block contains two slices, and each slice contains multiple
MULT18X18D and ALU54B units. Each unit configures each register to use
any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are
connected per unit (so for example, two MULTs in the same block could
connect their CLK0s to different external signals). However, the
hardware only has one actual port per block, so it's required that
all CLK0 signals within a block are the same.
Because the packer is in general allowed to combine two unrelated units
into one block, it may end up combining units that use different signals
for the same port, which would eventually have caused a router failure.
This commit adds validity checks which ensure only unique signals are
used per block, and adds remapping so that conflicting signals are
automatically reassigned when possible and required.
