Miodrag Milanovic
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796d648995
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Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui
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2019-12-28 13:54:06 +01:00 |
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Miodrag Milanovic
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50f87a6024
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add newline at eof
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2019-12-28 13:51:02 +01:00 |
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Miodrag Milanovic
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b271e59472
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Add global wires
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2019-12-15 17:20:48 +01:00 |
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Miodrag Milanovic
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ebbfb6375d
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more new wires added
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2019-12-14 09:18:24 +01:00 |
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Miodrag Milanovic
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2a5f0bbd28
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new wires in db
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2019-12-13 18:24:49 +01:00 |
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Miodrag Milanovic
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c0585e98eb
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added siologic
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2019-12-13 14:32:27 +01:00 |
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Miodrag Milanovic
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16f6aaa68c
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Add many new wires
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2019-12-13 14:01:28 +01:00 |
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David Shah
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bac8335222
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ecp5: Add constids for new timing cell types
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-26 20:50:50 +01:00 |
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Miodrag Milanovic
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d1feb2aa2d
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display horizontal wires, add some globals to list
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2019-10-23 18:17:08 +02:00 |
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Miodrag Milanovic
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e69bb4c077
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Simplify layout of elements
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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8c79044d43
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more wires between switchboxes
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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28d0313ccc
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Less types needed
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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eafc0e4e9e
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Added type to wire
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2019-10-20 09:41:48 +02:00 |
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David Shah
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a14555c8d1
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ecp5: Add IDDR71B support
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 12:07:56 +01:00 |
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David Shah
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9b83e67460
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ecp5: Preparations for new IO bels
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 10:55:10 +01:00 |
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David Shah
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2da41a66c7
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ecp5: Conservative analysis of comb DSP timing
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-08 15:09:54 +01:00 |
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David Shah
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63e1f02c65
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ecp5: Helper functions for DQS and ECLK
Signed-off-by: David Shah <dave@ds0.me>
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2019-02-24 10:28:25 +01:00 |
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David Shah
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e929d221f3
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ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG
Signed-off-by: David Shah <dave@ds0.me>
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2019-02-08 12:34:22 +00:00 |
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David Shah
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b12a8c1a30
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ecp5: Add {S}IOLOGIC constids and cell
Signed-off-by: David Shah <dave@ds0.me>
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2018-12-12 19:08:48 +00:00 |
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David Shah
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18813f2056
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ecp5: Adding real timing data to database
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-16 13:26:28 +00:00 |
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David Shah
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e9fe444dc7
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ecp5: Adding ancillary DCU bels
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-15 11:30:27 +00:00 |
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David Shah
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cc9fb1497d
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ecp5: Groundwork for DCU support
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-15 11:30:27 +00:00 |
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David Shah
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e005cc6754
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ecp5: Add PLL support
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-31 19:52:41 +00:00 |
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David Shah
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1a06f4b2bd
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ecp5: Adding DSP support
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-21 20:07:18 +01:00 |
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David Shah
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48f08e6d39
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ecp5: Adding constids for blockram
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-05 10:54:30 +01:00 |
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David Shah
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97b12fa741
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ecp5: Add DCC Bels, fix global router post-rebase
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-09-29 16:09:21 +01:00 |
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David Shah
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a3ae3f9791
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ecp5: Update to use const IdStrings in place of PortPin/BelType
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-08-08 19:08:43 +02:00 |
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