caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3,720 Commits 22 Branches 7 Tags 17 MiB
b4602ae5bf
Commit Graph

251 Commits

Author SHA1 Message Date
gatecat
b4602ae5bf interchange: Search backwards for IO macro placements, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-26 16:01:53 +01:00
gatecat
f61fa73b77 interchange: Check IO validity after all are placed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-23 17:09:39 +01:00
gatecat
5212e38512
Merge pull request #757 from antmicro/lut-mapping-cache 
interchange: Add caching of site LUT mapping solution
 2021-07-22 14:09:40 +01:00
Maciej Kurc
580a45485a Added an option to disable the LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-22 14:07:35 +02:00
Maciej Kurc
8fc16a57c9 Added more code comments, formatted the code 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-22 12:59:10 +02:00
Maciej Dudek
0e838c3cea Add dummy function to parse creat_clock in XDC files 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-21 18:43:11 +02:00
gatecat
f3be638ea9
Merge pull request #767 from YosysHQ/gatecat/ic-pref-const 
interchange: Fix preferred constant handling when canInvert
 2021-07-20 12:04:12 +01:00
gatecat
ffd97945ba interchange: Fix preferred constant handling when canInvert 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-20 10:42:04 +01:00
Maciej Kurc
ccf2bb123c Added computing and reporting LUT mapping cache size 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 15:53:00 +02:00
Maciej Kurc
c95aa86a8e Fixed assertion typos 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 15:16:31 +02:00
Maciej Kurc
857961a6bb Migrated C arrays to std::array containers. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 14:55:45 +02:00
Maciej Kurc
0336f55b16 LUT mapping ceche optimizations 2 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:55:19 +02:00
Maciej Kurc
044c9ba2d4 LUT mapping cache optimizations 1 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:28:40 +02:00
Maciej Kurc
d52516756c Working site LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 12:51:28 +02:00
Alessandro Comodi
7edfcc3bfa interchange: disallow pseudo-pip on same nets if tile has luts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-15 16:06:00 +02:00
Maciej Dudek
9190bda27d [interchange] Update chipdb and python-fpga-interchange versions 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-14 17:19:30 +02:00
Alessandro Comodi
7abfeb11c3 interchange: xdc and place constr: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 17:17:57 +02:00
Alessandro Comodi
3de0be7c06 interchange: xdc: add get_cells command 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 16:45:11 +02:00
Alessandro Comodi
d9668df818 interchange: add constraints constraints application routine 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 16:45:08 +02:00
gatecat
f03abe14d1 interchange: Skip IO ports in dedicated routing check 
These have already been dealt with in arch_pack_io

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-12 11:43:18 +01:00
gatecat
8604b03008 interchange: Debug IO port validity check failures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-12 11:40:23 +01:00
gatecat
96a5885051 interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-12 11:30:21 +01:00
Alessandro Comodi
fbd291deaf interchange: update chipdb version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-08 16:51:23 +02:00
Alessandro Comodi
dc0819b01a interchange: reduce run-time to check dedicated interconnect 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-08 16:51:23 +02:00
gatecat
31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:38:08 +01:00
gatecat
f64d06fa02 interchange: Improve search for PAD-attached bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:13:50 +01:00
Alessandro Comodi
6edc11de4d interchange: tests: add obuftds test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-06 09:57:26 +01:00
Alessandro Comodi
888a2462af interchange: phys: skip only nets writing on disconnected out ports 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-02 16:12:53 +02:00
gatecat
55c663f7ac
Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const 
interchange: Handle canInvert PIPs when processing preferred constants
 2021-07-01 15:28:24 +01:00
gatecat
74ffe2c543 interchange: Handle canInvert PIPs when processing preferred constants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:47:02 +01:00
gatecat
f17643bc08 interchange: Handle case where routing source is a node 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:19:10 +01:00
gatecat
ddff2e2e5e
Merge pull request #744 from YosysHQ/gatecat/const-in-macro 
interchange: Fix handling of constants in macros
 2021-07-01 13:12:38 +01:00
gatecat
79ab283890
Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports 
interchange: Reserve site ports only reachable from dedicated routing
 2021-07-01 13:12:29 +01:00
gatecat
006a40a353 interchange: Fix handling of constants in macros 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:45:23 +01:00
Alessandro Comodi
dd7cfccbae interchange: phys: do not output nets which have no users 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-01 12:36:05 +02:00
gatecat
523ffbaa37 interchange: Reserve site ports only reachable from dedicated routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:28:12 +01:00
Alessandro Comodi
cfbd1dfa4d interchange: fix dedicated interconnect exploration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-30 20:04:23 +02:00
gatecat
b3882f8324 interchange: Fix dedicated interconnect check when site is the same 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:48:51 +01:00
gatecat
ef18590043 interchange: Place IO macro content based on routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:37:30 +01:00
gatecat
2476f116bb interchange: Track the macros that cells have been expanded from 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-29 14:48:47 +01:00
gatecat
78c965141f
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output 
interchange: Allow site wires driven by more than one bel
 2021-06-28 16:27:04 +01:00
gatecat
65a4bce9ad interchange: Allow site wires driven by more than one bel 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:55:56 +01:00
gatecat
980a7013d2 interchange: Handle disconnected bel pins in dedicated interconnect 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:45:27 +01:00
Alessandro Comodi
0344fdcf8d interchange: arch: move macro expansion step before ios packing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 16:42:05 +02:00
gatecat
ded32f3390
Merge pull request #728 from YosysHQ/gatecat/nexus-ram 
interchange/nexus: Add RAM techmap rule and a RAM test
 2021-06-15 17:39:23 +01:00
Alessandro Comodi
f9054190fd interchange: fix phys net writer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-15 14:07:20 +02:00
gatecat
3e8f08895b nexus: Add modified version of RAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 11:07:40 +01:00
gatecat
f42ad6b90c nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 09:21:53 +01:00
gatecat
377f56c151 interchange: Cope with undriven nets in more places 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-14 10:58:42 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00