caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4,277 Commits 22 Branches 7 Tags 17 MiB
b5d30c7387
Commit Graph

284 Commits

Author SHA1 Message Date
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:20:39 +01:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
09e388f453 netlist: Add PseudoCell API 
When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.

The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
 2022-07-08 14:30:57 +02:00
Maciej Kurc
d75c45c63f Added fallback to VCC as the preferred constant if the architecture does not specify one. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-12 11:55:16 +02:00
Maciej Kurc
7c7a4f0959 Added tying unused LUT pins to preferred constant instead of Vcc 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:34 +02:00
Maciej Kurc
aafe1a176c Generalized representation of unused LUT pins connections 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:30 +02:00
Krzysztof Boronski
8c0dbdb218 interchange: Don't hold reference to visit in global routing 
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
 2022-03-11 07:53:42 -06:00
gatecat
df7e26c1aa clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-09 17:12:59 +00:00
Alessandro Comodi
b5d6fc8ed7 interchange: lut map cache: remove hardcoded values 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-04 16:53:24 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
Alessandro Comodi
a3ba83fce3 interchange: fix uninitialized memory bug in cluster placement 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-01 11:53:56 +02:00
gatecat
19afb07370 interchange: Fix compile warnings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-28 10:11:09 +01:00
Maciej Dudek
ea489f6d93 Fix small isses and code formatting 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-27 16:16:33 +02:00
Maciej Dudek
439ae9609b Break up macro_cluster_placement into smaller functions 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-24 11:07:37 +02:00
Maciej Dudek
44def159cc Fix AC-3 algorithm 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 17:15:09 +02:00
Maciej Dudek
b12119d8e8 Improve macro cluster placement 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
94acf7a797 Change Cluster placement algorithm 
Use physical placement from device DB
It should reduce runtime

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
3cd459912a Adding MacroCell placement 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
fdcfe8cd81 Adding support for MacroCells 2021-09-23 15:43:23 +02:00
Alessandro Comodi
258b46125f interchange: xdc: add more not_implemented commands 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-08 15:15:58 +02:00
Alessandro Comodi
46fc902bcf interchange: xdc: add common not_implemented function 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-07 16:47:37 +02:00
gatecat
d4a14a0d04 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-06 13:29:52 +01:00
Alessandro Comodi
e0950408d5 interchange: clusters: fix other cluster allowance checks in same site 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:44:36 +02:00
Alessandro Comodi
2df931f7db interchange: entirely disable cache when binding site routing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:08:46 +02:00
Alessandro Comodi
78bf5796db interchange: disallow placing cells on sites with clusters 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-27 13:47:10 +02:00
gatecat
eb6817c259
Merge pull request #780 from YosysHQ/gatecat/fix-io-inv 
interchange: Search backwards for IO macro placements, too
 2021-07-26 16:58:00 +01:00
gatecat
b4602ae5bf interchange: Search backwards for IO macro placements, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-26 16:01:53 +01:00
gatecat
c74f0d3239 interchange: Don't attempt to import instances as modules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-26 15:36:20 +01:00
gatecat
f61fa73b77 interchange: Check IO validity after all are placed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-23 17:09:39 +01:00
gatecat
5212e38512
Merge pull request #757 from antmicro/lut-mapping-cache 
interchange: Add caching of site LUT mapping solution
 2021-07-22 14:09:40 +01:00
Maciej Kurc
580a45485a Added an option to disable the LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-22 14:07:35 +02:00
Maciej Kurc
8fc16a57c9 Added more code comments, formatted the code 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-22 12:59:10 +02:00
Maciej Dudek
0e838c3cea Add dummy function to parse creat_clock in XDC files 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-21 18:43:11 +02:00
gatecat
f3be638ea9
Merge pull request #767 from YosysHQ/gatecat/ic-pref-const 
interchange: Fix preferred constant handling when canInvert
 2021-07-20 12:04:12 +01:00
gatecat
ffd97945ba interchange: Fix preferred constant handling when canInvert 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-20 10:42:04 +01:00
Maciej Kurc
ccf2bb123c Added computing and reporting LUT mapping cache size 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 15:53:00 +02:00
Maciej Kurc
c95aa86a8e Fixed assertion typos 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 15:16:31 +02:00
Maciej Kurc
857961a6bb Migrated C arrays to std::array containers. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 14:55:45 +02:00
Maciej Kurc
0336f55b16 LUT mapping ceche optimizations 2 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:55:19 +02:00
Maciej Kurc
044c9ba2d4 LUT mapping cache optimizations 1 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:28:40 +02:00
Maciej Kurc
d52516756c Working site LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 12:51:28 +02:00
Alessandro Comodi
7edfcc3bfa interchange: disallow pseudo-pip on same nets if tile has luts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-15 16:06:00 +02:00
Maciej Dudek
9190bda27d [interchange] Update chipdb and python-fpga-interchange versions 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-14 17:19:30 +02:00
Alessandro Comodi
7abfeb11c3 interchange: xdc and place constr: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 17:17:57 +02:00