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603 Commits

Author SHA1 Message Date
David Shah
64d3e3e1e8 ecp5: Use dedicated routing for ECLKs where possible 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-14 19:20:13 +01:00
Miodrag Milanovic
96c14abd1f Add TRELLIS_PROGRAM_PREFIX 2020-04-11 22:05:30 +02:00
David Shah
a8111bba83 ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 08:25:16 +01:00
David Shah
ced336492c ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-09 21:36:27 +01:00
David Shah
396dfb7d5e
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database 
Add support for REGMODE to DP16KD
 2020-04-07 20:02:29 +01:00
Ross Schlaikjer
3aecb3b08c
No need to fetch context 2020-04-07 14:44:19 -04:00
Ross Schlaikjer
fc591421f9
Change assert to error 2020-04-07 14:42:27 -04:00
Ross Schlaikjer
e46b990251
Rearrange bool algebra 2020-04-07 14:31:17 -04:00
Ross Schlaikjer
3257bdc8a1
Actually just move all the logic to ArchInfo 2020-04-07 14:11:49 -04:00
Ross Schlaikjer
0bdf1e05f1
Extract regmode configuration to ArchInfo 2020-04-07 14:03:55 -04:00
Ross Schlaikjer
c007463168
Change timing database lookup based on REGMODE value 2020-04-07 13:48:21 -04:00
David Shah
e8933f8519
Merge pull request #419 from garytwong/handle-opendrain 
Handle OPENDRAIN attribute.
 2020-04-07 09:44:40 +01:00
Gary Wong
ec1eea9990 Fix assertion failure on invalid LOCATE input. 
Trying to parse this invalid LPF syntax:

    LOCATE COMP "a" SITE "A1"
    IOBUF PORT "a" IO_TYPE=LVCMOS33;

(note missing semicolon on first line) gives an assertion failure in
strip_quotes, because the fifth token is scanned as "A1"IOBUF (without
a trailing quote).

Avoid the problem by detecting extraneous input and issuing a more
specific error.
 2020-04-05 21:42:45 -06:00
Gary Wong
31e9fffadd Handle OPENDRAIN attribute. 2020-04-03 17:59:19 -06:00
David Shah
f9a76c56f7 ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pin 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-03 09:53:14 +01:00
Gary Wong
8cc6a2fae5 Remove comment about the USRMCLK primitive being untested. 
Tested and verified working: the trivial configuration:

    module USRMCLK( USRMCLKI, USRMCLKTS );
        input USRMCLKI, USRMCLKTS;
    endmodule

    module top( input clk );
        reg[ 24:0 ] count = 0;

        always @( posedge clk ) begin
            count <= count + 1'b1;
        end

        USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) );
    endmodule

produces the expected output (toggling at high frequency, toggling
tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate
clock.  See https://bayimg.com/AAnNKAAGO for an example.  The top
(magenta) trace is the MCLK line.
 2020-04-02 21:35:35 -06:00
Martin
707289c8d6 Enum/int compatibility for EHXPLLL parameters 
- Lattice component EHXPLLL parameter compatibility, allowing to
  pass an int parameter for the enum (as expected by trellis tile)
  e.g. CLKOP_TRIM_DELAY : integer := 0;
 2020-04-02 14:25:00 +02:00
David Shah
3b49c20f43 ecp5: Proper support for '12k' device 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-13 11:22:11 +00:00
David Shah
bb73580209
Merge pull request #400 from YosysHQ/dave/tri-fixes 
Improve handling of unused inout port bits
 2020-03-10 13:50:59 +00:00
David Shah
751f4556fd ecp5: Fix differential inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-08 11:32:34 +00:00
Sylvain Munaut
054be6fb67 build: Default the ECP5 and iCE40 roots to the install prefix 
If the user specifies a custom install prefix, chances are icestrom/trellis
are also in that prefix rather than the hardcoded /usr/local

Fixes #351

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-03 15:32:10 +01:00
David Shah
9aa22433ff Improve handling of unused inout port bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-25 14:26:47 +00:00
Sebastian Birke
2c938e0e8b Rename cmake path variable TRELLIS_ROOT to TRELLIS_INSTALL_PREFIX 2020-02-04 18:19:45 +01:00
Jared Boone
1b560ae44c CMake: Changing the definition of TRELLIS_ROOT to point to root of lib, share containing trellis libs and data 
two other commit message of squashed commits:
CMake: Search for user lib inside trellis instead of libtrellis

CMake: Fix missing path component for share contents
 2020-02-04 18:19:45 +01:00
David Shah
1ceffbe0bc
Merge pull request #391 from YosysHQ/router2-upstream 
Upstreaming router2
 2020-02-04 16:08:08 +00:00
David Shah
b4d029a55c
Merge pull request #385 from YosysHQ/router1-arc-fixes 
Fixes for partial reconfig demo
 2020-02-03 13:55:07 +00:00
David Shah
2248e07b66 router2: Improve flow and log output 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 13:46:05 +00:00
David Shah
7123209324 Allow selection of router algorithm 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:54:38 +00:00
David Shah
ad1cc12df1 router2: Make magic numbers configurable 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
5e1aac67db ecp5: Improve bounding box accuracy 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
d2c77fd9ae ecp5: router2 main rename 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
abdaa9c8a1 ecp5: Router2 test integration 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:30 +00:00
Erika
9185c85a54 python: Expose PlaceStrength enum and isValidBelForCell on ecp5 
Signed-off-by: Erika <rrika9@yahoo.com>
 2020-01-26 20:32:02 +00:00
David Shah
3b5e64e8c6 ecp5: Fix tieoff of unused DELAY signals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-21 19:02:26 +00:00
David Shah
7c81d4e630 ecp5: Add SPICB0 IO support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 20:30:14 +00:00
David Shah
9dc8e1e35d ecp5: Don't reroute existing globals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 14:58:38 +00:00
Miodrag Milanovic
714769e1b8 Few more caught by clang 2020-01-18 15:58:09 +01:00
David Shah
54c1bc1538
Merge pull request #382 from YosysHQ/ecp5-psuedodiff 
ecp5: Add support for top pseudo diff outputs
 2020-01-16 09:38:00 +00:00
David Shah
f513d5fff4 ecp5: Add support for top pseudo diff outputs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-15 11:43:12 +00:00
Larry Doolittle
eba6ea53f8 More adjustments to .bba file locations 
Follows PM discussion with Marcus Comstedt.
Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases,
  so all cases become compatible with read-only access to git tree.
Only known down-side is inefficiency when building out-of-tree for multiple architectures;
  people following that use case should consider using PREGENERATED_BBA_PATH.
It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake,
  but that would have to be addressed by someone more skilled in Cmake and MSVC.
 2020-01-14 12:28:40 -08:00
Larry Doolittle
b6a7b607fd Remove barrier to out-of-tree builds 
With this change, nextpnr can build successfully (and run correctly) using the git tree as a read-only reference.
No change in behavior observed for in-tree builds.
 2020-01-12 21:11:56 -08:00
Miodrag Milanovic
fb5480cde3 clangformat 2019-12-28 15:02:13 +01:00
Miodrag Milanovic
59f4755e8f made most of frequent numbers constants 2019-12-28 15:01:36 +01:00
Miodrag Milanovic
6cca93543b move constants to gfx.cc 2019-12-28 14:27:14 +01:00
Miodrag Milanovic
6ebe2fd034 remove synt example 2019-12-28 14:08:58 +01:00
Miodrag Milanovic
796d648995 Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui 2019-12-28 13:54:06 +01:00
Miodrag Milanovic
50f87a6024 add newline at eof 2019-12-28 13:51:02 +01:00
David Shah
0d43aff268 ecp5: Always promote IOLOGIC SCLK to global 
Fixes #374

Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 15:53:00 +00:00
David Shah
fe40094216 Preserve hierarchy through packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
b100087024 python: Add bindings for hierarchy structures 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
b6e2159cec Work around Qt MOC issue with IdString enums 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:32:23 +00:00
Miodrag Milanovic
a05954249a optimize and set order 2019-12-20 14:02:00 +01:00
Miodrag Milanovic
c26c5e7b8e clang format 2019-12-20 09:07:03 +01:00
Miodrag Milanovic
e4210e7fd3 Add all missing wires 2019-12-20 09:05:58 +01:00
Miodrag Milanovic
b271e59472 Add global wires 2019-12-15 17:20:48 +01:00
Miodrag Milanovic
d5174110fa more pips on connection box 2019-12-15 10:57:24 +01:00
Miodrag Milanovic
f2b8e347a9 cleanup and formating 2019-12-15 10:43:30 +01:00
Miodrag Milanovic
2872b500e3 make it more simetric 2019-12-15 10:33:12 +01:00
Miodrag Milanovic
bbc05f3113 optimize and add some missing pips 2019-12-15 10:07:55 +01:00
Miodrag Milanovic
3d42097e9d cleanup 2019-12-15 09:45:09 +01:00
Miodrag Milanovic
fa55a826b2 cleanup wire 2019-12-15 09:26:25 +01:00
Miodrag Milanovic
436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic
fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic
cce27e72f0 lot more pips 2019-12-14 16:29:25 +01:00
Miodrag Milanovic
abf9bc3bb9 fixes and more pips 2019-12-14 16:10:41 +01:00
Miodrag Milanovic
d42ecc081e pips for alu, mult and memory 2019-12-14 13:00:09 +01:00
Miodrag Milanovic
7e7e20742d pips for ios 2019-12-14 12:30:04 +01:00
Miodrag Milanovic
601360b73a propagate w and h 2019-12-14 10:56:26 +01:00
Miodrag Milanovic
e118e418e5 pips for other type of connection box 2019-12-14 09:39:41 +01:00
Miodrag Milanovic
ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic
19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic
6d005f38b5 add more 2019-12-13 19:44:49 +01:00
Miodrag Milanovic
2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic
c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic
16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic
7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic
275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic
401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic
76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic
b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah
349be76d26 ecp5: Add support for flipflops with preload 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 12:20:25 +00:00
Miodrag Milanovic
0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
David Shah
1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:56:04 +00:00
David Shah
ff30bc87fe ecp5: Fix placement of DDRDLLA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:50:13 +00:00
David Shah
b4e9f5c3a6
Merge pull request #356 from YosysHQ/ecp5-ff-density 
ecp5: Improve flipflop packing density
 2019-11-27 11:22:14 +00:00
David Shah
98fe4438f1 ECP5 support is no longer experimental 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 16:10:53 +00:00
David Shah
aee2e01983 ecp5: Improve flipflop packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-20 18:22:22 +00:00
David Shah
08cf545d9b Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr" 
This reverts commit 6a7d1fe53d, reversing
changes made to c3d4117a21.
 2019-11-20 17:10:11 +00:00
David Shah
67e216f8fb ecp5: Add support for promotion of LSRs to global network 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-19 14:08:35 +00:00
David Shah
c3d4117a21 ecp5: Fix handling of custom DEL_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 22:03:11 +00:00
David Shah
36c0ff2dbc ecp5: Fix dynamic DELAYF control 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 20:58:08 +00:00
David Shah
9a848d9d76 ecp5: Add logic utilisation before packing statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 16:54:42 +00:00
David Shah
d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf 
Improve handling of top level IO and add SDF support
 2019-11-18 14:28:40 +00:00
Miodrag Milanovic
da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic
2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic
522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic
6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic
afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic
74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic
43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00