gridDimX and gridDimY are not initialized explicitly, which leads to
effects when the design is reloaded, say, from the GUI.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.
For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).
The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)
This commit does not yet disable the very first regular expression check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Both the mode used by yosys and all Gowin primitive modes are supported.
- The ALU always starts with a zero slice.
- The maximum length of the ALU chain is limited to one line of the chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Specifying pin placement with this notation (e.g. IOR4B) allows
to use the same constraint file without changes for different
packages and even different families.
The vendor router also understands this notation.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
