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Author SHA1 Message Date
gatecat
73a7406211
Merge pull request #871 from yrabbit/english 
gowin: Fix spelling of messages
 2021-12-14 08:54:09 +00:00
YRabbit
fdf26e698f gowin: Fix spelling of messages 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-12-14 14:09:27 +10:00
gatecat
f36188f2e1 ecp5: LUT permutation support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-13 20:22:06 +00:00
gatecat
8720d79f21
Merge pull request #868 from mkj/mkj/chipdb-16bit 
ecp5: Reduce some chipdb fields from 32 to 16 bit
 2021-12-13 15:02:38 +00:00
Matt Johnston
90b0e90bbe ecp5: Reduce some chipdb fields sizes 
This reduces the final binary size by ~7 MB for 85k
 2021-12-13 11:48:50 +08:00
gatecat
a933f82845 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 18:49:37 +00:00
gatecat
0dafcc44ff router2: Improve reservation debug logging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 18:49:14 +00:00
gatecat
c76e1be397
Merge pull request #867 from mkj/mkj/routerspeed2 
Improvements to ecp5 router speed
 2021-12-12 15:37:36 +00:00
gatecat
cb362c2256
Merge pull request #869 from YosysHQ/gatecat/mistral-route-fix 
mistral: DATAIN and DATAOUT of GPIO have swapped
 2021-12-12 14:59:34 +00:00
Matt Johnston
fc5b34254f ecp5: Keep "visited" local 
Otherwise it keeps growing boundless and slows down small arcs
 2021-12-12 22:09:11 +08:00
Matt Johnston
80dd442412 ecp5: Use a vector rather than dict 
This improves router1 performance vs the default dict
Using it for wire2net, pip2net, wire_fanout
 2021-12-12 22:09:11 +08:00
gatecat
61597e14a7 mistral: Bump CI version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:55:06 +00:00
gatecat
78905c3ecf mistral: DATAIN and DATAOUT of GPIO have swapped 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:03:28 +00:00
gatecat
1c8d4d6460 Merge branch 'master' of github.com:YosysHQ/nextpnr 2021-12-12 13:02:58 +00:00
gatecat
35feb7ebba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:02:39 +00:00
gatecat
21fc372a9d
Merge pull request #865 from yrabbit/ALU-head-at-zero 
gowin: BUGFIX. Place the ALU head in sliсe 0 only
 2021-12-12 13:00:38 +00:00
gatecat
3c8af04ca5 router2: Error instead of hang in case of reservation conflicts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:00:04 +00:00
YRabbit
ecf3027a4d
Merge branch 'YosysHQ:master' into ALU-head-at-zero 2021-12-12 07:43:14 +10:00
gatecat
62fcf944f9
Merge pull request #866 from YosysHQ/gatecat/mistral-include-tools 
mistral: Add 'tools' dir to include path
 2021-12-11 20:05:48 +00:00
gatecat
df061b1a9c mistral: Add 'tools' dir to include path 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-11 19:07:30 +00:00
YRabbit
e0ab7bf6c1 gowin: BUGFIX. Place the ALU head in sliсe 0 only 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-12-11 19:10:02 +10:00
gatecat
fd2d4a8f99
Merge pull request #863 from antmicro/pack_lutff 
nexus: LUT and FF clustering
 2021-11-24 17:16:38 +00:00
Maciej Kurc
41accf84ce Added checking if all FFs added to an existing cluster have matching configuration 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-23 15:16:26 +01:00
Maciej Kurc
238da79e52 Fixed potential issues with carry-chain cluster expansion, added a parameter controlling the ratio of FFs that got glued to carry-chain clusters. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 13:13:28 +01:00
Maciej Kurc
5bc97c94ae Added appending FFs to other existing LUT cluster types (carry, widefn) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc
086bcf0615 Added an option to control LUT and FF packing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc
d97f93ee88 Added clustering free LUTs and FFs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
gatecat
f5cc959c4e
Merge pull request #862 from DX-MON/master 
common: Improved the random seed initialisation for the context
 2021-11-19 21:45:07 +00:00
dx-mon
b3edf81f6c
common: Improved the random seed initialisation for the context 2021-11-19 09:39:10 -05:00
gatecat
b7207b0885
Merge pull request #859 from yrabbit/gowin-packages 
gowin: Add partnumbers and packages to the chipdb
 2021-11-07 08:12:12 +00:00
YRabbit
deb14762aa gowin: Check the chipdb version 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-11-07 09:05:34 +10:00
YRabbit
2a27085ecb gowin: use latest Apycula release 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-11-07 07:33:47 +10:00
YRabbit
19911ae3a7 Merge branch 'master' into gowin-packages 2021-11-06 22:17:31 +10:00
gatecat
1615b0a500
Merge pull request #857 from YosysHQ/gatecat/ecp5-ff-iodel 
ecp5: Fix packing of IOFF with IODELAYs
 2021-11-05 23:04:29 +00:00
gatecat
ce030a474c ecp5: Fix packing of IOFF with IODELAYs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-11-05 15:16:43 +00:00
YRabbit
74b4f69728 gowin: Use speed from chip base. 
Another simplification of the input regular expression, now
the speed is taken from the base.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-11-05 17:02:45 +10:00
YRabbit
0e8a2999bd gowin: Add partnumbers and packages to the chipdb 
Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)

This commit does not yet disable the very first regular expression check.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-11-04 18:55:00 +10:00
gatecat
06d58e6eed
Merge pull request #855 from galibert/master 
mistral: Sync with yet another reorganization
 2021-10-28 11:06:32 +01:00
Olivier Galibert
d51c559ab8 mistral: Sync with yet another reorganization 2021-10-28 11:00:44 +02:00
gatecat
80a14592a0
Merge pull request #852 from yrabbit/pr-gowin-alu 
gowin: Add ALU support.
 2021-10-22 16:08:35 +01:00
YRabbit
e9f3946d58 gowin: Explicitly initialize the y in the cluster 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-22 23:27:36 +10:00
YRabbit
f52fd6a272 gowin: Add ALU support. 
- Both the mode used by yosys and all Gowin primitive modes are supported.
  - The ALU always starts with a zero slice.
  - The maximum length of the ALU chain is limited to one line of the chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-22 14:41:18 +10:00
gatecat
013f3e0b39 interchange: Bump prjoxide version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-20 13:50:33 +01:00
gatecat
840aee7e0e
Merge pull request #851 from galibert/master 
mistral: Use the iterators
 2021-10-19 22:06:18 +01:00
Olivier Galibert
a0f1522167 Normalize formatting 2021-10-19 22:36:25 +02:00
Olivier Galibert
8d330f1dc7 mistral: Use the iterators 2021-10-19 22:25:55 +02:00
gatecat
3b99db294f
Merge pull request #848 from galibert/master 
mistral: Support the new routes-to-bin intermediate tool generation
 2021-10-17 19:02:25 +01:00
Olivier Galibert
d90de7f696 Sync mistral version in CI 2021-10-17 19:12:26 +02:00
gatecat
6bd1ab41b7
Merge pull request #849 from galibert/cyclonev-oscillator 
mistral: Add internal oscillator support
 2021-10-17 15:42:30 +01:00
Olivier Galibert
f88c119461 mistral: Add internal oscillator support 2021-10-17 14:26:24 +02:00