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Commit Graph

531 Commits

Author SHA1 Message Date
Miodrag Milanovic
2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic
c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic
16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic
7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic
275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic
401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic
76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic
b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah
349be76d26 ecp5: Add support for flipflops with preload 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 12:20:25 +00:00
Miodrag Milanovic
0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
David Shah
1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:56:04 +00:00
David Shah
ff30bc87fe ecp5: Fix placement of DDRDLLA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:50:13 +00:00
David Shah
b4e9f5c3a6
Merge pull request #356 from YosysHQ/ecp5-ff-density 
ecp5: Improve flipflop packing density
 2019-11-27 11:22:14 +00:00
David Shah
98fe4438f1 ECP5 support is no longer experimental 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 16:10:53 +00:00
David Shah
aee2e01983 ecp5: Improve flipflop packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-20 18:22:22 +00:00
David Shah
08cf545d9b Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr" 
This reverts commit 6a7d1fe53d, reversing
changes made to c3d4117a21.
 2019-11-20 17:10:11 +00:00
David Shah
67e216f8fb ecp5: Add support for promotion of LSRs to global network 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-19 14:08:35 +00:00
David Shah
c3d4117a21 ecp5: Fix handling of custom DEL_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 22:03:11 +00:00
David Shah
36c0ff2dbc ecp5: Fix dynamic DELAYF control 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 20:58:08 +00:00
David Shah
9a848d9d76 ecp5: Add logic utilisation before packing statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 16:54:42 +00:00
David Shah
d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf 
Improve handling of top level IO and add SDF support
 2019-11-18 14:28:40 +00:00
Miodrag Milanovic
da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic
2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic
522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic
6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic
afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic
74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic
43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic
9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic
f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah
21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:27:51 +00:00
David Shah
58b7cb920f ecp5: Fix placement of ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:07:51 +00:00
David Shah
5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 22:21:18 +01:00
David Shah
bac8335222 ecp5: Add constids for new timing cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:50:50 +01:00
David Shah
475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah
36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic
49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic
d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
David Shah
b582ba810c ecp5: Make database build depend on constids.inc 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:29:07 +01:00
Miodrag Milanovic
0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic
847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic
e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eafc0e4e9e Added type to wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah
a22f86f861 ice40: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-19 13:01:00 +01:00
David Shah
cf5cbd1153 ecp5: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-18 15:58:57 +01:00
David Shah
8f86ccc412 ecp5: Add support for ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:52:31 +01:00
David Shah
f2fd1bf80a ecp5: Fix tristate IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:35:16 +01:00
David Shah
c6401413a4 ecp5: Add support for IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:23:35 +01:00
David Shah
a14555c8d1 ecp5: Add IDDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 12:07:56 +01:00
David Shah
21847a55e0 ecp5: Add ODDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 11:23:20 +01:00
David Shah
9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah
cba36239a4 ecp5: Fix parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-04 14:54:31 +01:00
David Shah
d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah
cb71b488ec
Merge pull request #332 from YosysHQ/dave/python-refactor 
Improving Python API and adding docs for it
 2019-09-19 20:15:42 +01:00
David Shah
8351ae275e Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-precompiled-bba 2019-09-19 16:02:10 +01:00
David Shah
f8719a5717
Merge pull request #330 from zeldin/bba 
bba: Default to native endian in bbasm
 2019-09-19 15:57:23 +01:00
Sean Cross
062091e9e4 ecp5: add support for PREGENERATED_BBA_PATH 
Support pre-generated bba files to speed up compiling on Windows
and get it compiling on Darwin.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 11:32:44 +08:00
David Shah
d5e4986e1b python: Refactor out bindings shared between ECP5 and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 16:15:07 +01:00
David Shah
c2299c8972 python: Fix getWireBelPins 
Fixes #327

Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 15:59:16 +01:00
Marcus Comstedt
2f9b04fd56 CMake: Generate chipdbs in build tree when building out-of-tree 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 13:42:17 +02:00
Marcus Comstedt
3d9ce8836c bba: Require explicit endianness flag, and supply it 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 12:30:03 +02:00
David Shah
bc6b47efe0
Merge pull request #329 from YosysHQ/dave/net_aliases 
json: Add support for net aliases
 2019-09-13 19:01:26 +01:00
David Shah
95540763b9 json: Add support for net aliases 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 17:27:15 +01:00
David Shah
2ace9b5ad3 ecp5: Move clock constraints across IO and DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 16:50:07 +01:00
Sean Cross
f98960b936 ecp5: use $PYTHON_EXECUTABLE for python path 
Sometimes the python executable might have a different name.  Cmake
sets the $PYTHON_EXECUTABLE variable to point to the binary path,
so use this variable.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-09 22:10:51 +08:00
David Shah
04be9a71f9 ecp5: Add support for clock gating with DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 10:45:12 +01:00
David Shah
9f9920f92b ecp5: Add full part name to bitstream header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 14:36:20 +01:00
David Shah
78f86ce67a ecp5: Add GSR/SGSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:14:41 +01:00
Arnaud Durand
a26c9bb6d9 Rename clock restriction attribute to "noglobal" 2019-08-24 18:09:42 +02:00
Arnaud Durand
a947f09bfb Restrict clock promotion to global 2019-08-22 00:43:03 +02:00
David Shah
c70f87e4c5
Merge pull request #309 from YosysHQ/dsptiming 
ecp5: Conservative analysis of comb DSP timing
 2019-08-09 10:27:15 +01:00
David Shah
c9969c1593 Add deprecation warning for default packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:35:55 +01:00
David Shah
f0abbc71b5 ecp5: Fix handling of missing ports in LUT permutation 
Fixes #310

Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:24:01 +01:00
David Shah
e55946bec7 clangfromat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:46:53 +01:00
David Shah
661237eb64 ecp5: Add --out-of-context for building hard macros 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:22:47 +01:00
David Shah
7126dacccd ecp5: Add a check for legacy parameter values 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 09:53:33 +01:00
David Shah
ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah
1839a3a770 Major Property improvements for common and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 14:52:15 +01:00
David Shah
d297a96dc1 ecp5: Fix missing LUT inputs, fixes #301 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-10 09:34:22 +01:00
David Shah
2da41a66c7 ecp5: Conservative analysis of comb DSP timing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 15:09:54 +01:00