caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3,564 Commits 22 Branches 7 Tags 17 MiB
b8a68f5f35
Commit Graph

3564 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
gatecat
b8a68f5f35 Using hashlib in timing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
f4fed62c05 Use hashlib in routers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat
dfe0ce599a Bump tests submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat
43b8dde923 Use hashlib in placers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:49 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
76ef768864 common: Import hashlib from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
589ca8ded5
Merge pull request #719 from YosysHQ/gatecat/mistral-llvm 
mistral: Fix nextpnr build with LLVM
 2021-06-02 11:56:45 +01:00
gatecat
cbedf52342 mistral: Fix nextpnr build with LLVM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 10:44:03 +01:00
gatecat
2bef7b5f7b clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 17:10:40 +01:00
gatecat
e5c8214f2c
Merge pull request #717 from YosysHQ/gatecat/timing-memory-fix 
timing: Fix use of uninitialised value
 2021-06-01 12:23:57 +01:00
gatecat
665ab09d20
Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40 
interchange: Add LIFCL-40 EVN tests
 2021-06-01 11:45:34 +01:00
gatecat
315a5733d2 timing: Fix use of uninitialised value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 11:40:55 +01:00
gatecat
0426ba4e87 interchange: Add LIFCL-40 EVN tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 09:52:40 +01:00
Miodrag Milanovic
24ae205f20 Fixed warnings in QtPropertyBrowser component 2021-05-31 16:48:25 +02:00
Miodrag Milanovic
473723b24a Fix hidpi, fixes #167, fixes #275, fixes #425 2021-05-31 16:20:43 +02:00
gatecat
bf67845df6
Merge pull request #714 from YosysHQ/gatecat/mistral-dis-compress 
mistral: Make RBF compression optional
 2021-05-30 16:18:07 +01:00
gatecat
eb2265a2bf mistral: Make RBF compression optional 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-30 15:50:12 +01:00
gatecat
e2b838a10a
Merge pull request #713 from YosysHQ/gatecat/version-bump 
interchange: Bump versions
 2021-05-27 11:59:51 +01:00
gatecat
ba69b35501 interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-27 11:21:34 +01:00
gatecat
e19d44ee20
Merge pull request #686 from YosysHQ/gatecat/interchange-macro 
interchange: Add macro expansion
 2021-05-21 11:05:57 +01:00
gatecat
ff48ad83be interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
bae83857a3 interchange: Add macro parameter mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
64f5b1d031 interchange: Don't error out on missing cell ports 
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
a146dbdb03 interchange: Add LUTRAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
2759480cb5 interchange: Preliminary implementation of macro expansion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
237b27e50b interchange: Add macro param map rules to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
012b60c9ca interchange: Add macro data to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
81818fd38c
Merge pull request #712 from YosysHQ/gatecat/rr-heatmap 
router2: Add heatmap by routing resource type
 2021-05-21 09:59:19 +01:00
gatecat
54b8364cea
Merge pull request #711 from acomodi/interchange-site-to-pseudo-pips 
interchange: phys: add site instance idstr for pseudo tile PIPs
 2021-05-20 19:45:27 +01:00
Alessandro Comodi
9dce00a4e7 gh-actions: interchange: use commit sha as cache key 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-20 19:57:03 +02:00
Alessandro Comodi
6e22a9ea97 bump interchange schema 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-20 19:24:53 +02:00
gatecat
1595c07260 router2: Add heatmap by routing resource type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-20 14:54:23 +01:00
Alessandro Comodi
84359f39c5 interchange: phys: add site instance idstr for pseudo tile PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-19 18:48:54 +02:00
gatecat
5a41d2070c Run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-16 16:25:05 +01:00
gatecat
179ae683cc
Merge pull request #708 from Ravenslofty/mistral-getchipname 
mistral: add getChipName
 2021-05-15 22:59:46 +01:00
Lofty
b81ba2d6c2 mistral: add getChipName 
Signed-off-by: Lofty <dan.ravensloft@gmail.com>
 2021-05-15 22:50:56 +01:00
gatecat
47b4e42b1c
Merge pull request #707 from gatecat/cyclonev 
mistral: Initial Cyclone V support
 2021-05-15 22:37:19 +01:00
gatecat
3eeb2b20eb Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 21:51:56 +01:00
gatecat
9d7f90dd89 mistral: Add MISTRAL_CLKBUF cell type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 21:28:48 +01:00
gatecat
6cef569155 ci: Use GH only for Mistral and fpga-interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 15:53:25 +01:00
gatecat
3bb94192d5 mistral: Tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b1e1492dac mistral: Make router2 the default 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
f318898474 router2: Hacky workaround for slow Cyclone V convergence 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
7fbfd98b8a mistral: Speed up bel binding and checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
34677d3883 mistral: Workaround for weird SCLR issue 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
9221acc9e2 mistral: Fix ENA and ACLR bitstream generation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
4d32c4f2fc mistral: Disable global buffers that are currently broken 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00