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Author SHA1 Message Date
gatecat
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi
ea9e12b6ae gh-actions: increase python-fpga-interchange tag version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:47 +02:00
Alessandro Comodi
dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat
b26088f940
Merge pull request #679 from YosysHQ/gatecat/disable-absl 
Hash table changes
 2021-04-14 12:19:10 +01:00
gatecat
b0f57d234f ci: Re-enable abseil for interchange CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:53 +01:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
2912860c97
Merge pull request #677 from YosysHQ/gatecat/ppip-no-input 
interchange: Allow pseudo-cells with no input pins
 2021-04-13 11:49:48 +01:00
gatecat
06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat
423da76ff2
Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash 
timing: Fix domain init when loops are present
 2021-04-13 10:34:14 +01:00
gatecat
ece10c3e04 timing: Fix domain init when loops are present 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 09:23:08 +01:00
gatecat
5cd2a7f9c2
Merge pull request #674 from adamgreig/heap-spreader-fix 
HeAP: Skip high-strength cells in both cell loops
 2021-04-12 14:16:22 +01:00
gatecat
dc6453b720
Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref 
fast_bels: Don't return pointer that might become invalid
 2021-04-12 13:54:11 +01:00
Adam Greig
2fdf41ac01
HeAP: Skip high-strength cells in both cell loops. 
Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
 2021-04-12 13:42:20 +01:00
gatecat
fc15105643 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:26:39 +01:00
gatecat
5b35329abb fast_bels: Don't return pointer that might become invalid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:23:41 +01:00
gatecat
b5731cee02
Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc 
interchange: Disambiguate cell and bel pins when creating Vcc ties
 2021-04-09 14:33:12 +01:00
gatecat
9cc09207fc
Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin 
interchange: Pin prjoxide commit in CI
 2021-04-09 11:37:54 +01:00
gatecat
7acef00443 interchange: Pin prjoxide commit 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 11:17:25 +01:00
gatecat
93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties 
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.

This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 10:26:32 +01:00
Miodrag Milanović
581682a08e
Merge pull request #667 from YosysHQ/fix_qt 
Add same fix as in issue #373
 2021-04-08 13:40:44 +02:00
Miodrag Milanovic
157cc1b60c Add same fix as in issue #373 2021-04-08 12:33:34 +02:00
gatecat
883ece6034
Merge pull request #665 from cr1901/optional-lto 
Add CMake option to enable IPO (enabled by default).
 2021-04-07 12:21:23 +01:00
William D. Jones
2cb2985539 Add CMake option to enable IPO (enabled by default). 2021-04-07 06:25:29 -04:00
gatecat
31eda82b3f
Merge pull request #659 from litghost/pseudo_pip_fixes 
[interchange] Pseudo pip fixes
 2021-04-06 20:08:37 +01:00
gatecat
8501098c16
Merge pull request #663 from litghost/fix_router2_without_bb 
Fix bug in router2 where router may give up too early.
 2021-04-06 19:35:55 +01:00
Keith Rothman
ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c43ad2fab6 Don't fail-fast for GH actions to allow for easier CI debugging. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
3200026e1f [interchange] Remove requirement to have wire_lut. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
8773c645ca [interchange] Prevent site router from generating incorrect LUTs. 
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal.  This case is now prevented by tying the
output of the LUT to an unused net.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c11ad31393 [interchange] Scale edge cost of pseudo pips. 
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h 
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
90aa1d3b7e [interchange] Disallow site edges during general routing. 
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
0d41fff3a7 [interchange] Add crude pseudo pip model. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
a519341112 Fix bug in router2 where router may give up too early. 
Was introduced in #612.  The logic before was intended to prevent the
router from terminating early when not using a bounding box, but the fix
in #612 simply removed that, meaning that the router might terminate
early incorrectly.  The solution here is to only use the toexplore
hysteric once a solution is found.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:22:47 -07:00
gatecat
ff449ca997
Merge pull request #661 from litghost/document_site_router 
[interchange] Add some documentation for the site router.
 2021-04-06 09:20:03 +01:00
gatecat
cf6833b9cd
Merge pull request #662 from litghost/fix_cirrus_ci 
Increase vCPU to 5 because of cirrus resource limit change.
 2021-04-06 09:18:30 +01:00
gatecat
8e0d8df791
Merge pull request #657 from acomodi/interchange-counter-multi-board 
interchange: counter: testing on multiple boards
 2021-04-06 08:12:02 +01:00
Keith Rothman
d399d3ae1b Increase vCPU to 5 because of cirrus resource limit change. 
Cirrus CI now requires that RAM (in GiB) be less than 4*vCPU.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-05 16:12:47 -07:00
Keith Rothman
4301e4705b [interchange] Add some documentation for the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-05 15:15:48 -07:00
gatecat
bb6079133c
Merge pull request #658 from litghost/increment_chipdb 
[interchange] Update to v6 of FPGA interchange chipdb.
 2021-04-02 09:46:21 +01:00
Keith Rothman
3a85088d66 [interchange] Update interchange CI for new chipdb change. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:59:48 -07:00
Keith Rothman
009d3b64b6 [interchange] Update to v6 of FPGA interchange chipdb. 
Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:24:06 -07:00
Alessandro Comodi
366f8782cb interchange: counter: testing on multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-01 10:23:07 +02:00
gatecat
ec98fee1ee
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake 
fpga_interchange: Add CMake support for Nexus/prjoxide
 2021-03-31 15:14:51 +01:00
gatecat
3678eff5dc interchange: Fix nexus cmake review comments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-31 10:11:09 +01:00
gatecat
edecc06fcf
Merge pull request #656 from litghost/fix_dedicated_interconnect_bug 
Fix bug where DedicateInterconnect incorrectly allows some placements.
 2021-03-30 22:36:51 +01:00
Keith Rothman
8675945b26 Fix bug where DedicateInterconnect incorrectly allows some placement. 
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 13:24:39 -07:00
gatecat
4dc45ffdc8
Merge pull request #653 from litghost/fix_site_pip_check 
[interchange] Fix site pip check for drivers.
 2021-03-30 18:50:16 +01:00
Keith Rothman
7e47af1085 [interchange] Fix site pip check for drivers. 
Previous code allowed router to entire sites with no sinks.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 10:04:18 -07:00