caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3,273 Commits 22 Branches 7 Tags 17 MiB
bac2a8ba02
Commit Graph

3273 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
gatecat
f0e30abf62 nexus: Fail gracefully when seeing special pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 12:15:58 +00:00
gatecat
8a4bf3a780 timing: Integration tweaks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 10:04:35 +00:00
gatecat
98d1c5a411 timing: Skip route delays for unplaced/nullptr cells 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:34:20 +00:00
gatecat
1ff2023f32 timing: Replace all users of criticality with new engine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:29:11 +00:00
gatecat
5f6aaa2475 timing: Use new engine in SA except for budget-based mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
ebc2527368 timing: Use new engine for HeAP 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
bbf5a7d461 timing: Add support for critical path printing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
e681e0f14c timing: Slack and criticality computation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
296e6d10c2 timing: Produce plausible Fmax figure 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
541376f8cc timing: Add Fmax printing for debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
16e7bba87b timing: Add backwards path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
0528ceead1 timing: Add forward path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
9c8d1bd6e3 timing: Compute domain pairs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
534e69fbff timing: Add port-domain tracking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
7a546b1554 timing: Add topological sort from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
d0772ce1e3 timing: Import cell delays to our own structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
fac6a6c068 timing: Data structures for STA rewrite 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
1aab019f1e
Merge pull request #608 from YosysHQ/gatecat/lifcl-17 
Fix global normalisation for LIFCL-17
 2021-03-03 15:19:17 +00:00
gatecat
685cc23b94 nexus: Fix global handling for LIFCL-17 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-03 13:46:05 +00:00
gatecat
fba71bd182 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-03 10:39:47 +00:00
gatecat
6e38e236f8
Merge pull request #604 from litghost/add_counter_test 
Add counter test for FPGA interchange
 2021-03-03 07:06:07 +00:00
gatecat
27fbee5233
Merge pull request #605 from litghost/add_placement_sanity_check 
Add placement sanity check in placer_heap.
 2021-03-02 08:27:12 +00:00
Keith Rothman
392156c250 Correct spelling of RAII and add missing check in unlock_early. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 13:11:04 -08:00
Keith Rothman
0afa0da19f Add absl::flat_hash_map. 
This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:55:54 -08:00
Keith Rothman
99a2262d61 Use scope in router1/2 and placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:43:39 -08:00
gatecat
6ff02248a3
Merge pull request #606 from pepijndevos/gowin_fixes 
Gowin DFF fixes
 2021-02-28 18:20:11 +00:00
Pepijn de Vos
354d497a57 only one type of dff per slice 2021-02-28 17:48:05 +01:00
gatecat
6689bfe923
Merge pull request #603 from litghost/fix_trival_bad_swap 
Prevent trival misplacements in placer1.
 2021-02-26 20:06:02 +00:00
Keith Rothman
77a5a60a66 Fix latent bug with context locking in placer HeAP. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:40:58 -08:00
Keith Rothman
7878561970 Add placement sanity check in placer_heap. 
Also check return of placer1_refine.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:27:43 -08:00
Keith Rothman
71b92cb813 Update FPGA interchange README. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
78748a67be For now just return false in the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
9cbfd0b967 Add counter test. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
c65ba121e0 Prevent trival misplacements in placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 10:59:48 -08:00
gatecat
396af7470b
Merge pull request #602 from YosysHQ/gatecat/remove-unused-constr 
Remove unused advanced timing constraint API
 2021-02-26 11:03:21 +00:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API 
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-26 10:07:00 +00:00
gatecat
89928a0e6b
Merge pull request #599 from litghost/allow_router2_to_use_preroutes 
Allow router2 to use routed but not fixed arcs.
 2021-02-26 09:44:03 +00:00
gatecat
49fae99063
Merge pull request #601 from YosysHQ/no-default-Werror 
cmake: Don't enable any -Werror flags without opt-in
 2021-02-26 08:06:07 +00:00
whitequark
a0af4d8768
cmake: Don't enable any -Werror flags without opt-in. 2021-02-26 00:33:05 +00:00
Keith Rothman
c64a910151 Allow router2 to use routed but not fixed arcs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-25 15:55:29 -08:00
gatecat
de107da5b3
Merge pull request #598 from YosysHQ/gatecat/compiler-flags 
Tighten up compiler flags
 2021-02-25 16:16:37 +00:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
17183fff05 cmake: Enable -Wextra, and -Werror in some cases 
-Werror is not enabled by default, except on CI and for a few specific common traps, to avoid the inevitable breakages when new compiler versions add new diagnostics.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 11:05:26 +00:00
gatecat
ab8dfcfba4
Merge pull request #591 from litghost/add_constant_network 
Add constant network support to FPGA interchange arch
 2021-02-25 10:22:45 +00:00
gatecat
e2cdaa653c
Merge pull request #597 from litghost/add_dynamic_bitarray 
Add dynamic bitarray to common library.
 2021-02-24 18:22:16 +00:00
Keith Rothman
e0a4af09ed Bump tests submodule. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:23 -08:00
Keith Rothman
6d193ffd8b Fix some bugs found in review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:06 -08:00
gatecat
4026082470 docs/archapi: Typo fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-24 15:28:33 +00:00
Keith Rothman
3650294e51 Add dynamic bitarray to common library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 15:43:47 -08:00