Commit Graph

95 Commits

Author SHA1 Message Date
Keith Rothman
db12a83ced Add pseudo pip data to chipdb (with schema bump).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:33:12 +00:00
Keith Rothman
2cd5bacca0 Refactor header structures in FPGA interchange Arch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-19 21:36:06 -07:00
Keith Rothman
351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 18:49:12 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange.
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
5574455d2a Working FF example now that constant merging is done.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
46b38f8a40 Fix reference copy.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
3ccb164f2a Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
15459cae91 Initial working constant network support!
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
40df4f4f65 Add initial constant network support to FPGA interchange arch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:08:54 -08:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
Keith Rothman
c21e23b3eb Fix sign mismatch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 14:08:22 -08:00
Keith Rothman
4766e889c0 Add some utility methods for site instance access.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:26:52 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
Keith Rothman
7c1544f4d8 Continue fixes.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
Keith Rothman
c385321248 Add initial site router.
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
gatecat
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only
Add Cell -> BEL Pin maps to FPGA interchange arch.
2021-02-17 10:16:45 +00:00
Keith Rothman
bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps.
This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-16 09:37:19 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
Keith Rothman
664407089b Add FPGA interchange frontend and backend.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2
Support for cell pin to bel pin mappings
2021-02-15 09:38:22 +00:00
Keith Rothman
a0bd313139 Add FPGA interchange XDC parser.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 11:54:54 +00:00
D. Shah
9deb9e6e85 interchange: Base on ArchAPI
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:41:03 +00:00
Keith Rothman
a0ee42833b Add RelSlice::ssize and use it when comparing with signed ints.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-05 10:12:13 -08:00
Keith Rothman
9557047e5e Move all string data into BBA file.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-05 09:22:55 -08:00
Keith Rothman
ca32e935a6 Use RelSlice instead of RelPtr in cases where sizes are present.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:34 -08:00
Keith Rothman
f1ee2fde58 Update APIs to conform to style guide.
- Change non-Arch methods to snake_case
 - Adds some utility functions to for accessing bel_data.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:34 -08:00
Keith Rothman
9afa8a9bea Remove unused method getReservedWireNet.
This was a holdover from the nextpnr-xilinx arch.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
22c3c9c303 Update copywrite headers.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
0b911e484c Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
78737ab01d Update FPGA interchange to use IdStringList.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
4a62c8c2eb Start adding data for placement constraint solving.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
5c16c5024d Debug BEL bucket data.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
cd41c4001e Add initial updates to FPGA interchange arch for BEL buckets.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
67dc19bb57 Address review comments.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
5a89dc58e1 Fix BBA import bugs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
1dd24f6461 Assorted fixes to new FPGA interchange based arch.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
6e68e8f097 Initial compiling version.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:32 -08:00
Keith Rothman
561b519716 Initial FPGA interchange (which is just a cut-down xilinx arch).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:32 -08:00