Commit Graph

150 Commits

Author SHA1 Message Date
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
David Shah
fa77a5ae4a clangformat
Signed-off-by: David Shah <dave@ds0.me>
2019-06-24 11:43:01 +01:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Simon Schubert
88eeafae12 ice40: add RGB_DRV/LED_DRV_CUR support for u4k 2019-06-10 14:04:25 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
07b21c5129 Add vcc and gnd nets and cells only if needed 2019-06-07 13:58:21 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Miodrag Milanovic
eff1a1341a Revert "Do not add VCC if not used, loading json works"
This reverts commit f1b3a14bc2.
2019-06-02 08:51:32 +02:00
Miodrag Milanovic
d5d8213871 Added support for attributes/properties types 2019-06-01 15:52:32 +02:00
Miodrag Milanovic
f1b3a14bc2 Do not add VCC if not used, loading json works 2019-05-31 13:38:18 +02:00
Sylvain Munaut
e17299a1ca ice40: Add support for HFOSC trimming
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-05-13 12:52:58 +02:00
Sylvain Munaut
6387a3d33e ice40: Only create padin gbuf for PLLs if global output actually used
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-17 14:06:23 +02:00
Sylvain Munaut
9dd68aa0e2 ice40: Take placed SB_GBs into account when placing PLLs
Because the PLLs drive global networks, we need to account for
already existing and placed SB_GBs when trying to place/pack them.

Theses can be user instanciated SB_GBs with BEL attribute, or
SB_GB_IOs that got converted during the IO packing.

This patch assumes that:
 - If a PLL is used the output A global network is always used, even
   if there is no connection to the global output pin
 - If a PLL with a singe output is used, then the B output global
   network is still free to be used by whatever.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-16 10:12:28 +02:00
Sylvain Munaut
6cb4e2e83b ice40/pack: During IO packing, remove any unused input connection
This is mostly for the benefit of PLL placement because the D_IN_x
ports are used for other purposes when PLL is enabled so we need to
make sure nothing is connected there already. (even an unused net is
too much)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-11 13:52:23 +02:00
David Shah
d27ec2cd15 ice40: Don't constrain to a PLL bel that has already been used
Fixes #258

Signed-off-by: David Shah <dave@ds0.me>
2019-04-01 12:25:32 +01:00
Sylvain Munaut
d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-25 23:48:59 +01:00
David Shah
054be887ae ice40: PLLs can't conflict with themselves
Fixes error building testcase from #145

Signed-off-by: David Shah <dave@ds0.me>
2019-02-09 19:27:52 +00:00
David Shah
170bf8a5ec ice40: Don't create PLLOUT_B buffer for single-output PLL variants
Signed-off-by: David Shah <dave@ds0.me>
2019-02-09 10:41:22 +00:00
David Shah
265fa1be16
Merge pull request #211 from smunaut/ice40_ram_attrs
ice40/pack: Copy attributes to packed cell
2019-01-21 11:10:38 +00:00
Sylvain Munaut
b274a8f8f0 ice40/pack: Copy attributes to packed RAM cells
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-01-19 15:49:21 +01:00
Sylvain Munaut
830d462f92 ice40: Add error message if a selected site is not Global Buffer capable
... rather than assert()-out during the call to getWireBelPins() call

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-01-18 17:53:24 +01:00
David Shah
4444a39fd4 ice40: Improve handling of unconstrained IO
Signed-off-by: David Shah <dave@ds0.me>
2018-12-26 16:00:19 +00:00
David Shah
75335d4e1a ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs
Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-20 18:50:34 +00:00
David Shah
144363693d ice40: Report error for unsupported PLL FEEDBACK_PATH values
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:29:33 +00:00
whitequark
7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block.
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
2018-12-01 22:27:04 -03:00
David Shah
8af367ad0a ice40: Add a warning for unconstrained IO
Signed-off-by: David Shah <dave@ds0.me>
2018-11-29 19:35:19 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh
ice40: raise CE global promotion threshold
2018-11-29 09:12:47 +00:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:43 +01:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion
Signed-off-by: David Shah <dave@ds0.me>
2018-11-27 19:06:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit !
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
Signed-off-by: David Shah <dave@ds0.me>
2018-11-24 17:49:26 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
35e9ec7737 ice40: Minor fix in predicate checking for logic port
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-16 16:36:57 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00