Commit Graph

74 Commits

Author SHA1 Message Date
Eddie Hung
3a5665c1cb Speedup placement slightly using bel_to_loc 2018-09-03 21:00:11 -07:00
Eddie Hung
6d17810dde Merge fixes 2018-09-03 13:20:19 -07:00
Eddie Hung
c128df127b Do not consider route-through for CLB tiles 2018-09-03 13:17:16 -07:00
Eddie Hung
d2597bcd8d Fix segments 2018-09-03 00:10:16 -07:00
Eddie Hung
7e693ff27d Precompute pips too 2018-09-02 19:06:20 -07:00
Eddie Hung
ca7eef26ac Wires now encapsulate segments 2018-09-02 16:57:11 -07:00
Eddie Hung
b658a39d73 IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky 2018-08-21 22:18:00 -07:00
Eddie Hung
3e1085ecb5 Combine IOB33S and IOB33M 2018-08-20 19:25:54 -07:00
Eddie Hung
a87f26b254 Update comment 2018-08-19 19:41:24 -07:00
Eddie Hung
a7ccc01c45 Use getBelType() 2018-08-19 17:38:55 -07:00
Eddie Hung
17918b5992 Fix for multiple id_SLICE_LUT6 per actual SLICE 2018-08-17 23:05:12 -07:00
Eddie Hung
b8b9813056 id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation() 2018-08-14 08:42:27 -07:00
Eddie Hung
72c785db0e Convert to use torc_info 2018-08-12 22:09:16 -07:00
Eddie Hung
7b15569c69 Use general pin names for QUARTER_SLICE 2018-08-12 20:29:04 -07:00
Eddie Hung
56b7299cca {SLICEL,SLICEM} -> QUARTER_SLICE 2018-08-12 20:21:03 -07:00
Eddie Hung
f6f20dce0c Rename ddb to torc 2018-08-12 19:20:13 -07:00
Eddie Hung
57c273898c Finishes placement now 2018-08-11 22:24:13 -07:00
Eddie Hung
67a0fa11e6 Enable timing 2018-08-11 21:36:23 -07:00
Eddie Hung
2bc7ffc2ea WIP 2018-08-11 21:13:49 -07:00
Eddie Hung
8cddc49abc Starts placement onto all Xilinx sites 2018-08-11 18:52:48 -07:00
Eddie Hung
45009ac09d Remove timing, remove wires 2018-08-11 17:08:50 -07:00
Eddie Hung
8357417787 Load Torc DDB 2018-08-11 15:53:55 -07:00
Eddie Hung
6425032ec4 Rip out ice40 stuff, put xc7z020 in 2018-08-11 15:00:31 -07:00
Eddie Hung
d53658a079 Copy ice40 into xc7 2018-08-11 14:35:49 -07:00