Eddie Hung
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84485152cc
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Remove some more ice40 stuff
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2018-12-28 15:20:51 -08:00 |
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Eddie Hung
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ede0e93206
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Merge branch 'xc7' into xc7_gui
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2018-12-27 20:53:15 -08:00 |
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Eddie Hung
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a630758ca7
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Cleanup
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2018-12-26 18:14:23 -08:00 |
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Eddie Hung
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097062c5cb
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Remove pip_to_dst_wire lookup
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2018-12-08 22:49:39 -08:00 |
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Eddie Hung
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8c44888466
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Fix delay prediction
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2018-12-06 17:40:15 -08:00 |
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Eddie Hung
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66f22150b1
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Improve estimateDelay for global clocks
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2018-12-06 16:49:35 -08:00 |
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Eddie Hung
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5f75a8447f
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Merge in vx980t support
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2018-12-06 20:07:51 +00:00 |
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Miodrag Milanovic
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105c148848
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Made Pip and Wires trees work
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2018-11-28 19:49:28 +01:00 |
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Miodrag Milanovic
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bfa2157ae6
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compile fix for gui and proper size
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2018-11-28 17:59:58 +01:00 |
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Miodrag Milanovic
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f2fecc3c69
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make gui run
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2018-11-28 17:04:26 +01:00 |
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Eddie Hung
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440802bf9d
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Add support for serialization of torc_info
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2018-11-27 17:55:31 -08:00 |
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Eddie Hung
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662733c171
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Remove methods
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2018-11-27 14:12:25 -08:00 |
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Eddie Hung
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a0b6d3b19b
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clangformat
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2018-11-27 12:28:48 -08:00 |
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Eddie Hung
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ae9ccfa5ad
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Refactor torc_info constructor
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2018-11-27 12:28:21 -08:00 |
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Eddie Hung
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c3dc8696eb
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Fix getDelayFromNS()
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2018-11-20 15:00:09 -08:00 |
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Eddie Hung
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ab9cb99f52
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Arch::getPipDelay() returns delay of dst wire; Arch::getWireDelay() to return nothing
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2018-11-20 14:52:01 -08:00 |
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Eddie Hung
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18cee5d279
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More changes for upstream
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2018-11-20 14:26:29 -08:00 |
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Eddie Hung
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75654a69f0
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Fix LUT input delays, speedup construct_wire_to_delay?
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2018-11-11 14:15:11 -08:00 |
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Eddie Hung
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83117bef66
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Add missing APIs needed for router_improve
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2018-11-11 10:19:17 -08:00 |
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Eddie Hung
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5c56fab0ab
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[xc7] Add torc_info->site_index_to_bel lookup; also fix Arch::getBelByName()
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2018-11-03 15:56:06 -07:00 |
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Eddie Hung
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aa7f7d6a97
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clangformat
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2018-11-03 15:18:26 -07:00 |
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Eddie Hung
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db6e81d6c3
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Populate Arch::getWireDelay()
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2018-09-04 10:11:10 -07:00 |
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Eddie Hung
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d78f5a1d5b
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Build a pip_to_dst_wire lookup to speedup routing
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2018-09-03 22:59:34 -07:00 |
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Eddie Hung
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3a5665c1cb
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Speedup placement slightly using bel_to_loc
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2018-09-03 21:00:11 -07:00 |
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Eddie Hung
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d2597bcd8d
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Fix segments
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2018-09-03 00:10:16 -07:00 |
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Eddie Hung
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7e693ff27d
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Precompute pips too
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2018-09-02 19:06:20 -07:00 |
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Eddie Hung
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ca7eef26ac
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Wires now encapsulate segments
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2018-09-02 16:57:11 -07:00 |
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Eddie Hung
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a7ccc01c45
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Use getBelType()
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2018-08-19 17:38:55 -07:00 |
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Eddie Hung
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17918b5992
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Fix for multiple id_SLICE_LUT6 per actual SLICE
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2018-08-17 23:05:12 -07:00 |
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Eddie Hung
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b8b9813056
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id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation()
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2018-08-14 08:42:27 -07:00 |
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Eddie Hung
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72c785db0e
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Convert to use torc_info
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2018-08-12 22:09:16 -07:00 |
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Eddie Hung
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56b7299cca
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{SLICEL,SLICEM} -> QUARTER_SLICE
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2018-08-12 20:21:03 -07:00 |
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Eddie Hung
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f6f20dce0c
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Rename ddb to torc
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2018-08-12 19:20:13 -07:00 |
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Eddie Hung
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57c273898c
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Finishes placement now
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2018-08-11 22:24:13 -07:00 |
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Eddie Hung
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2bc7ffc2ea
|
WIP
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2018-08-11 21:13:49 -07:00 |
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Eddie Hung
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8cddc49abc
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Starts placement onto all Xilinx sites
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2018-08-11 18:52:48 -07:00 |
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Eddie Hung
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45009ac09d
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Remove timing, remove wires
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2018-08-11 17:08:50 -07:00 |
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Eddie Hung
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8357417787
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Load Torc DDB
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2018-08-11 15:53:55 -07:00 |
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Eddie Hung
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6425032ec4
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Rip out ice40 stuff, put xc7z020 in
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2018-08-11 15:00:31 -07:00 |
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Eddie Hung
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d53658a079
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Copy ice40 into xc7
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2018-08-11 14:35:49 -07:00 |
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