caiyu/nextpnr
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2,016 Commits 22 Branches 7 Tags 17 MiB
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165 Commits

Author SHA1 Message Date
Eddie Hung
d7dd945f55 Overwrite COMPENSATION attribute on MMCME2_ADV to "INTERNAL" 2018-11-29 16:32:08 -08:00
Eddie Hung
d8b6b231de Move required attributes to pack 2018-11-29 15:38:28 -08:00
Eddie Hung
6985e80c01 Merge branch 'xc7' of gitlab.com:eddiehung/nextpnr into xc7 2018-11-29 13:32:32 -08:00
Miodrag Milanovic
535fc953d4 Use site x location to determine if it is one block or other 2018-11-29 12:44:02 -08:00
Eddie Hung
9f03d9eed3 Add PLL to bring 125MHz clock to 60MHz for picorv32 2018-11-29 12:25:39 -08:00
Miodrag Milanovic
1f387d44fb Use site x location to determine if it is one block or other 2018-11-29 21:12:56 +01:00
Miodrag Milanovic
b7a06a02c4 Display slices 2018-11-29 20:54:46 +01:00
Eddie Hung
4161856d49 Add support for MMCME2_ADV 2018-11-28 22:34:22 -08:00
Miodrag Milanovic
105c148848 Made Pip and Wires trees work 2018-11-28 19:49:28 +01:00
Miodrag Milanovic
bfa2157ae6 compile fix for gui and proper size 2018-11-28 17:59:58 +01:00
Miodrag Milanovic
f2fecc3c69 make gui run 2018-11-28 17:04:26 +01:00
Eddie Hung
13e7798b34 Fix #endif placement 2018-11-27 18:11:19 -08:00
Eddie Hung
212b03999b Gzip the torc_info data 2018-11-27 18:08:03 -08:00
Eddie Hung
440802bf9d Add support for serialization of torc_info 2018-11-27 17:55:31 -08:00
Eddie Hung
662733c171 Remove methods 2018-11-27 14:12:25 -08:00
Eddie Hung
a0b6d3b19b clangformat 2018-11-27 12:28:48 -08:00
Eddie Hung
ae9ccfa5ad Refactor torc_info constructor 2018-11-27 12:28:21 -08:00
Eddie Hung
fc015d28d3 Fix pip indexing, do not allow fabric to connect to CLK (only global network can) 2018-11-20 17:41:46 -08:00
Eddie Hung
c3dc8696eb Fix getDelayFromNS() 2018-11-20 15:00:09 -08:00
Eddie Hung
ab9cb99f52 Arch::getPipDelay() returns delay of dst wire; Arch::getWireDelay() to return nothing 2018-11-20 14:52:01 -08:00
Eddie Hung
fa3e390e5f Add TODO 2018-11-20 14:43:21 -08:00
Eddie Hung
18cee5d279 More changes for upstream 2018-11-20 14:26:29 -08:00
Eddie Hung
e19ad23ef4 Merge branch 'xc7-router_improve' into xc7 2018-11-13 17:21:46 -08:00
Eddie Hung
9a498c26d1 Update picorv32.sh 2018-11-13 11:07:43 -08:00
Eddie Hung
bccf95296c Add picorv32.pcf 2018-11-13 11:07:08 -08:00
Eddie Hung
ca94aa1915 Reduce blinky.sh freq to 150MHz 2018-11-13 10:11:27 -08:00
Eddie Hung
fa3d366ddb Add missing operator needed by router_improve 2018-11-13 10:10:57 -08:00
Eddie Hung
d5ca744ca0 Fix typo 2018-11-13 09:10:14 -08:00
Eddie Hung
72a16004e1 Divide columns by 2 to get better X estimate for tiles 2018-11-13 09:01:24 -08:00
Eddie Hung
ec96897c1d Ahead of LUT input swapping, assign LUT<6 from A6 downwards 2018-11-11 14:21:06 -08:00
Eddie Hung
75654a69f0 Fix LUT input delays, speedup construct_wire_to_delay? 2018-11-11 14:15:11 -08:00
Eddie Hung
53f025c03f Improved delay estimator 2018-11-11 12:56:52 -08:00
Eddie Hung
83117bef66 Add missing APIs needed for router_improve 2018-11-11 10:19:17 -08:00
Eddie Hung
99f5836b0e Add some cell delays 2018-11-10 19:55:22 -08:00
Eddie Hung
a0c6c64be7 blinky.v to not instantiate PS7, blink more slowly/predictably 2018-11-10 18:50:43 -08:00
Eddie Hung
533c730418 Update without $iob suffix 2018-11-10 18:49:58 -08:00
Eddie Hung
10d6db6d94 Do not add "$iob" suffix 2018-11-10 18:48:46 -08:00
Eddie Hung
f6bdd92640 Implement Arch::getPipName() and remove debug/verbose before routing 2018-11-10 16:11:38 -08:00
Eddie Hung
3d8b88deef blinky to instantiate PS7 so that reconfiguring from Linux doesn't kill PS 2018-11-10 12:53:41 -08:00
Eddie Hung
2b2254f514 Add support for PS7 blocks 2018-11-10 12:53:41 -08:00
Eddie Hung
3b86c3a381 blinky to instantiate PS7 so that reconfiguring from Linux doesn't kill PS 2018-11-10 12:52:52 -08:00
Eddie Hung
3576509684 Add support for PS7 blocks 2018-11-10 12:51:56 -08:00
Eddie Hung
4619b2d82f Disable debug/verbose flag before routing 2018-11-09 17:09:25 -08:00
Eddie Hung
31ae470414 Adapt blinky for xc7 2018-11-09 17:07:23 -08:00
Eddie Hung
c6f66b4468 Adapt blinky for xc7 2018-11-09 17:05:55 -08:00
Eddie Hung
a5be1bbe6e [xc7] Fix LUT mask logic; also add attributes for IGNORE0 and {CE,S,IGNORE}1 2018-11-05 08:21:32 -08:00
Eddie Hung
e53f8364ec [xc7] Also ignore PIN token lines for PCF 2018-11-05 08:21:14 -08:00
Eddie Hung
f67cf32d0d [xc7] PCF reader to ignore lines with NET token 2018-11-04 22:14:10 -08:00
Eddie Hung
61939dca11 [xc7] blinky.sh to set freq 125 MHz and run trce 2018-11-04 22:13:51 -08:00
Eddie Hung
f1b454b96c [xc7] blinky.v to use led0-3, and just to be safe, set BUFGCTRL control 
inputs too
 2018-11-04 22:13:24 -08:00
Eddie Hung
42a1b1a750 [xc7] Add NET PERIOD constraint to blinky.pcf (for trce) 2018-11-04 22:12:43 -08:00
Eddie Hung
e137a9c507 [xc7] Add xdl and bitgen to blinky.sh 2018-11-03 16:12:11 -07:00
Eddie Hung
5c56fab0ab [xc7] Add torc_info->site_index_to_bel lookup; also fix Arch::getBelByName() 2018-11-03 15:56:06 -07:00
Eddie Hung
aa7f7d6a97 clangformat 2018-11-03 15:18:26 -07:00
Eddie Hung
d80b63cc55 [xc7] Re-enable PCF reading 2018-11-03 15:17:53 -07:00
Eddie Hung
4239e3668a [xc7] Make clg400 the default package (Zybo) 2018-11-03 15:02:09 -07:00
Eddie Hung
c6bf8aff43 [xc7] Fix timing analysis for constant drivers 2018-11-03 14:24:29 -07:00
Eddie Hung
8f1c91151b Revert "[xc7] Fix getPortTimingClass for IOBs" 
This reverts commit 5d9019994e.
 2018-11-03 13:30:58 -07:00
Eddie Hung
0e1c23a07b [xc7] blinky.v to only have 4 LEDs 2018-11-03 13:27:39 -07:00
Eddie Hung
5d9019994e [xc7] Fix getPortTimingClass for IOBs 2018-11-03 12:55:36 -07:00
Eddie Hung
324ff41f13 Fix Torc path 2018-11-03 12:10:21 -07:00
Eddie Hung
735c7c7c9c torc now expected to be /opt/torc 2018-11-03 11:41:36 -07:00
Eddie Hung
834f5f58c2 Fix wire delays, disable BUFG I->O routethrough 2018-09-05 22:24:46 -07:00
Eddie Hung
5214d1dbb5 Segment anchors may not be beginning of wires 2018-09-04 11:05:03 -07:00
Eddie Hung
d0916943c5 Extend delays to cover BYP and FAN 2018-09-04 10:41:32 -07:00
Eddie Hung
c7f0bdfc1b Move DelayInfo into loop 2018-09-04 10:35:12 -07:00
Eddie Hung
db6e81d6c3 Populate Arch::getWireDelay() 2018-09-04 10:11:10 -07:00
Eddie Hung
7da5e2b525 Reduce predictDelay/estimateDelay to 100ps per tile 2018-09-04 10:10:27 -07:00
Eddie Hung
d78f5a1d5b Build a pip_to_dst_wire lookup to speedup routing 2018-09-03 22:59:34 -07:00
Eddie Hung
30fe1f229a Set CE0INV and S0INV for BUFGCTRL; PRESELECT_I0 to be TRUE if not set 2018-09-03 22:25:05 -07:00
Eddie Hung
2eeb59d9f1 Re-enable routing 2018-09-03 22:24:59 -07:00
Eddie Hung
3a5665c1cb Speedup placement slightly using bel_to_loc 2018-09-03 21:00:11 -07:00
Eddie Hung
4f61d2dae7 Add yosys script 2018-09-03 19:23:36 -07:00
Eddie Hung
86fa032b63 picorv32_top to instantiate BUFGCTRL, and picorv32.sh to use picorv32.ys script 2018-09-03 19:23:00 -07:00
Eddie Hung
7f1c1ecaf0 blinky.v to instantiate BUFGCTRL correctly 2018-09-03 19:22:39 -07:00
Eddie Hung
bf5a4717f5 Add pips to XDL output 2018-09-03 13:40:52 -07:00
Eddie Hung
6d17810dde Merge fixes 2018-09-03 13:20:19 -07:00
Eddie Hung
c128df127b Do not consider route-through for CLB tiles 2018-09-03 13:17:16 -07:00
Eddie Hung
d2597bcd8d Fix segments 2018-09-03 00:10:16 -07:00
Eddie Hung
3f865f9049 Fix Arch::estimateDelay() 2018-09-02 23:38:53 -07:00
Eddie Hung
7e693ff27d Precompute pips too 2018-09-02 19:06:20 -07:00
Eddie Hung
ca7eef26ac Wires now encapsulate segments 2018-09-02 16:57:11 -07:00
Eddie Hung
df2f295545 Apparently netgen needs SYNC_ATTR to be set 2018-09-02 13:09:28 -07:00
Eddie Hung
82fbc551f8 Fix DRC errors 2018-08-21 22:58:20 -07:00
Eddie Hung
3a177c72c6 Preserve packed LUT name as LUT_NAME parameter 2018-08-21 22:24:14 -07:00
Eddie Hung
b658a39d73 IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky 2018-08-21 22:18:00 -07:00
Eddie Hung
5b6255abf1 Fix LUT masks, add speedgrade, fix IOB type 2018-08-20 21:50:06 -07:00
Eddie Hung
0a16e24c82 create_ice_cell -> create_xc7_cell 2018-08-20 19:29:04 -07:00
Eddie Hung
3e1085ecb5 Combine IOB33S and IOB33M 2018-08-20 19:25:54 -07:00
Eddie Hung
f7be783a32 Escape flop names as well 2018-08-20 19:21:53 -07:00
Eddie Hung
718f5b81f0 Escape colons in config names 2018-08-20 19:19:45 -07:00
Eddie Hung
699bd3ef5a Fix for leading '+', and use An for LUT masks 2018-08-19 22:31:50 -07:00
Eddie Hung
a87f26b254 Update comment 2018-08-19 19:41:24 -07:00
Eddie Hung
dcc08b27cc Output unrouted nets into XDL 2018-08-19 19:41:11 -07:00
Eddie Hung
07fb4702ce Populate LUT masks 2018-08-19 19:16:24 -07:00
Eddie Hung
a7ccc01c45 Use getBelType() 2018-08-19 17:38:55 -07:00
Eddie Hung
17918b5992 Fix for multiple id_SLICE_LUT6 per actual SLICE 2018-08-17 23:05:12 -07:00
Eddie Hung
d05ac75fda Add basics for XDL exporter 2018-08-17 21:52:34 -07:00
Eddie Hung
b8b9813056 id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation() 2018-08-14 08:42:27 -07:00
Eddie Hung
72c785db0e Convert to use torc_info 2018-08-12 22:09:16 -07:00