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574 Commits

Author SHA1 Message Date
Eddie Hung
4134bfa78e [timing] Resolve another merge conflict 2018-11-13 12:12:26 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Clifford Wolf
d0ae4c77be
Merge pull request #105 from YosysHQ/placer1_tmg_ignore 
[placer1] Ignore timing of TMG_IGNORE nets
 2018-11-13 18:48:59 +01:00
Eddie Hung
7402a4b955 [placer1] Tidy up logic 2018-11-13 09:26:28 -08:00
Clifford Wolf
caca485cff Minor router1 debug log improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 17:30:49 +01:00
Clifford Wolf
51b09f2407 Improve router1 debug output, switch to nameOf APIs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:29:33 +01:00
Clifford Wolf
e06eef375c Add more nameOf() convenience methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:08:44 +01:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
ba7a7a3733 timing: Fix compile warning 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
8af86ff37d ecp5: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
bd2b3e5e02 timing: Fix Fmax for clocks with mixed edge usage 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fad69d4930 timing: Don't include false startpoints in async paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
cba9b528e8 timing: Improve Fmax output and print cross-clock paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
143abc6034 timing: Multiple clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
3ca02cc55c Working on adding multiple domains to timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
b6312abc5d timing: Implementing parts of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
David Shah
83b1c43630 timing: Working on a timing constraint API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
David Shah
e0fe523606 Fix router1 check for ECP5 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 11:23:31 +00:00
Eddie Hung
7af788f9e3 [timing] Fix combinational -> combinatorial 2018-11-11 13:49:09 -08:00
Eddie Hung
32517dfb04 [timing] Better messaging for failed timing analysis, allow --force to 
continue
 2018-11-11 13:23:00 -08:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f9a5126338 Another router1 bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:50:42 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
ee8826b6e8 Ignore "duplicate" arcs in the same net in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 12:16:25 +01:00
Clifford Wolf
dac553cab4 Add some additional checks to router1 to find issues in input netlist 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 12:04:02 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Clifford Wolf
285bffeac5 Another bugfix in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 10:11:55 +01:00
Clifford Wolf
5cc9b9f61f Bugfix in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 10:02:32 +01:00
Eddie Hung
78b684bcf8 [placer1] Actually check for TMG_IGNORE! 2018-11-10 22:30:35 -08:00
Eddie Hung
200fb3f664 [placer1] Ignore timing of TMG_IGNORE nets 2018-11-10 20:05:36 -08:00
Clifford Wolf
e7ae28cafe Minor improvements in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 00:29:25 +01:00
Clifford Wolf
5b8c8bb966 Some router1 cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 23:50:49 +01:00
Clifford Wolf
d904a37138 flush logs when throwing an assertion_failure 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 23:50:08 +01:00
Clifford Wolf
6b94102e5a Add checkers and assertions to router1 and other improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 21:14:50 +01:00
Clifford Wolf
97070486f0 Fixes and cleanups in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 14:00:36 +01:00
Clifford Wolf
c780ce584a Fix log msg typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 23:03:14 +01:00
Clifford Wolf
e312fc79bc Improve router console output 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 22:59:23 +01:00
Clifford Wolf
f0a3a272ca Fixes and improvements in new router 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 22:39:39 +01:00
Clifford Wolf
aeaa0552ba Essentially a rewrite router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 17:00:45 +01:00
Clifford Wolf
66dd17664c Merge branch 'master' of github.com:YosysHQ/nextpnr into router_improve 2018-11-09 12:57:14 +01:00
Eddie Hung
8258586c7d [common] placer to produce error when >1 cell->bel constraint 2018-11-08 16:21:31 -08:00
Mateusz Zalega
d03291eeb1 gui: improved FPGAViewWidget::paintGL() performance 
Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking
the most time during paintGL() calls. I've been able to take the CPU usage
down to about 1/4 of its previous values by caching elements in VBOs and
updating them only after subsequent calls to renderGraphicElement().

Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com>
 2018-10-23 15:43:51 +02:00
David Shah
cdc9e0e81c
Merge pull request #92 from YosysHQ/python-cmdline 
Allow running Python scripts for all points in flow
 2018-10-21 10:08:04 +01:00
David Shah
b53a4862db
Merge pull request #89 from YosysHQ/ecp5_bram 
ECP5 BRAM support
 2018-10-17 11:14:27 +01:00
David Shah
7c9ab173da common: Allow running Python scripts for all points in flow 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-17 10:51:23 +01:00