Eddie Hung
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5c56fab0ab
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[xc7] Add torc_info->site_index_to_bel lookup; also fix Arch::getBelByName()
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2018-11-03 15:56:06 -07:00 |
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Eddie Hung
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aa7f7d6a97
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clangformat
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2018-11-03 15:18:26 -07:00 |
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Eddie Hung
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4239e3668a
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[xc7] Make clg400 the default package (Zybo)
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2018-11-03 15:02:09 -07:00 |
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Eddie Hung
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c6bf8aff43
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[xc7] Fix timing analysis for constant drivers
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2018-11-03 14:24:29 -07:00 |
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Eddie Hung
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8f1c91151b
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Revert "[xc7] Fix getPortTimingClass for IOBs"
This reverts commit 5d9019994e.
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2018-11-03 13:30:58 -07:00 |
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Eddie Hung
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5d9019994e
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[xc7] Fix getPortTimingClass for IOBs
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2018-11-03 12:55:36 -07:00 |
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Eddie Hung
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324ff41f13
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Fix Torc path
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2018-11-03 12:10:21 -07:00 |
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Eddie Hung
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834f5f58c2
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Fix wire delays, disable BUFG I->O routethrough
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2018-09-05 22:24:46 -07:00 |
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Eddie Hung
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5214d1dbb5
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Segment anchors may not be beginning of wires
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2018-09-04 11:05:03 -07:00 |
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Eddie Hung
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d0916943c5
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Extend delays to cover BYP and FAN
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2018-09-04 10:41:32 -07:00 |
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Eddie Hung
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c7f0bdfc1b
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Move DelayInfo into loop
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2018-09-04 10:35:12 -07:00 |
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Eddie Hung
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db6e81d6c3
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Populate Arch::getWireDelay()
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2018-09-04 10:11:10 -07:00 |
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Eddie Hung
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d78f5a1d5b
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Build a pip_to_dst_wire lookup to speedup routing
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2018-09-03 22:59:34 -07:00 |
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Eddie Hung
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2eeb59d9f1
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Re-enable routing
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2018-09-03 22:24:59 -07:00 |
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Eddie Hung
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3a5665c1cb
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Speedup placement slightly using bel_to_loc
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2018-09-03 21:00:11 -07:00 |
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Eddie Hung
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6d17810dde
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Merge fixes
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2018-09-03 13:20:19 -07:00 |
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Eddie Hung
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c128df127b
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Do not consider route-through for CLB tiles
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2018-09-03 13:17:16 -07:00 |
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Eddie Hung
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d2597bcd8d
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Fix segments
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2018-09-03 00:10:16 -07:00 |
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Eddie Hung
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7e693ff27d
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Precompute pips too
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2018-09-02 19:06:20 -07:00 |
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Eddie Hung
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ca7eef26ac
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Wires now encapsulate segments
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2018-09-02 16:57:11 -07:00 |
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Eddie Hung
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b658a39d73
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IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky
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2018-08-21 22:18:00 -07:00 |
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Eddie Hung
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3e1085ecb5
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Combine IOB33S and IOB33M
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2018-08-20 19:25:54 -07:00 |
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Eddie Hung
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a87f26b254
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Update comment
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2018-08-19 19:41:24 -07:00 |
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Eddie Hung
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a7ccc01c45
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Use getBelType()
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2018-08-19 17:38:55 -07:00 |
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Eddie Hung
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17918b5992
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Fix for multiple id_SLICE_LUT6 per actual SLICE
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2018-08-17 23:05:12 -07:00 |
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Eddie Hung
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b8b9813056
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id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation()
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2018-08-14 08:42:27 -07:00 |
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Eddie Hung
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72c785db0e
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Convert to use torc_info
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2018-08-12 22:09:16 -07:00 |
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Eddie Hung
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7b15569c69
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Use general pin names for QUARTER_SLICE
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2018-08-12 20:29:04 -07:00 |
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Eddie Hung
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56b7299cca
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{SLICEL,SLICEM} -> QUARTER_SLICE
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2018-08-12 20:21:03 -07:00 |
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Eddie Hung
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f6f20dce0c
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Rename ddb to torc
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2018-08-12 19:20:13 -07:00 |
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Eddie Hung
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57c273898c
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Finishes placement now
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2018-08-11 22:24:13 -07:00 |
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Eddie Hung
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67a0fa11e6
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Enable timing
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2018-08-11 21:36:23 -07:00 |
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Eddie Hung
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2bc7ffc2ea
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WIP
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2018-08-11 21:13:49 -07:00 |
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Eddie Hung
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8cddc49abc
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Starts placement onto all Xilinx sites
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2018-08-11 18:52:48 -07:00 |
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Eddie Hung
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45009ac09d
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Remove timing, remove wires
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2018-08-11 17:08:50 -07:00 |
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Eddie Hung
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8357417787
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Load Torc DDB
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2018-08-11 15:53:55 -07:00 |
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Eddie Hung
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6425032ec4
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Rip out ice40 stuff, put xc7z020 in
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2018-08-11 15:00:31 -07:00 |
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Eddie Hung
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d53658a079
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Copy ice40 into xc7
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2018-08-11 14:35:49 -07:00 |
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