Eddie Hung
699bd3ef5a
Fix for leading '+', and use An for LUT masks
2018-08-19 22:31:50 -07:00
Eddie Hung
a87f26b254
Update comment
2018-08-19 19:41:24 -07:00
Eddie Hung
dcc08b27cc
Output unrouted nets into XDL
2018-08-19 19:41:11 -07:00
Eddie Hung
07fb4702ce
Populate LUT masks
2018-08-19 19:16:24 -07:00
Eddie Hung
a7ccc01c45
Use getBelType()
2018-08-19 17:38:55 -07:00
Serge Bazanski
f3fac0b0ef
gui: fix #57
2018-08-19 23:39:27 +01:00
Serge Bazanski
8ed64450f3
Merge pull request #56 from YosysHQ/q3k/issue-55
...
ice40: make PLL packing more robust
2018-08-19 21:37:02 +01:00
Sergiusz Bazanski
1bf22a7f64
ice40: make PLL packing more robust
2018-08-19 21:30:55 +01:00
Miodrag Milanovic
a6d702d85d
fix zoom on elements, fixes #61
2018-08-19 20:54:41 +02:00
Clifford Wolf
634340cabb
Merge pull request #60 from YosysHQ/ice40ui
...
More iCE40 gfx
2018-08-19 18:44:25 +02:00
Clifford Wolf
801f630983
Add more missing iCE40 gfx (LP/HX is complete now)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-19 18:43:38 +02:00
David Shah
39e79db854
ecp5: clangformat
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-19 17:12:03 +01:00
David Shah
0f86d082e5
Merge pull request #59 from daveshah1/ecp5_timing
...
Simple timing model for ECP5
2018-08-19 17:11:34 +01:00
David Shah
1b3a201a54
ecp5: Fix delay heuristic
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-19 17:10:55 +01:00
David Shah
ec94848774
ecp5: Add cell delays
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-19 16:59:36 +01:00
Clifford Wolf
49d3857f97
Add iCE40 gfx for carry chain pips and LUT cascade pips
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-19 17:55:54 +02:00
Clifford Wolf
e45769292a
Fix iCE40 pip gfx for pips on the top edge of a switchbox
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-19 17:23:21 +02:00
Clifford Wolf
91c60ac667
Merge pull request #58 from YosysHQ/ice40ui
...
Add iCE40 gfx for span wires between IO tiles, including corners
2018-08-19 16:58:27 +02:00
Clifford Wolf
b7d4c7afd9
Add iCE40 gfx for IO span-4 corners
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-19 16:53:34 +02:00
Clifford Wolf
7cdafb8121
Add iCE40 gfx for span-4 wires between IO tiles
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-19 16:31:02 +02:00
David Shah
cdc9dc545e
ecp5: Add crude approximation of Pip delays
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-19 14:29:16 +01:00
David Shah
45bd0a8c72
Merge pull request #54 from daveshah1/ecp5_speedup
...
ecp5: Improving placement speed
2018-08-19 14:04:01 +01:00
David Shah
0b35cb4e60
ecp5: Flatten bel_to_cell for performance
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-18 19:04:32 +01:00
David Shah
72a9a475fa
ecp5: Speed up Bel availability/binding checks
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-18 18:36:13 +01:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate
...
Use settings for placer1 and router1
2018-08-18 19:25:19 +02:00
Clifford Wolf
1e8e873c9f
Merge pull request #53 from YosysHQ/archattr
...
Add Attributes on arch objects and improve iCE40 gfx (IO tiles, BRAM tiles)
2018-08-18 19:22:46 +02:00
David Shah
b8206d71ca
ecp5: Speedup placement using ArchCellInfo
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-18 18:14:18 +01:00
Clifford Wolf
060be78c09
Merge pull request #51 from YosysHQ/json-update
...
Json update
2018-08-18 17:21:15 +02:00
Clifford Wolf
a346793c19
Add iCE40 gfx for wires connecting fabric tiles and IO tiles
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-18 17:17:01 +02:00
Clifford Wolf
456a83430a
Improve iCE40 gfx for IO tiles and RAM tiles
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-18 16:20:33 +02:00
Clifford Wolf
5500cf3aff
Add ice40 wire attributes (grid position, segment list)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-18 14:14:27 +02:00
Clifford Wolf
74eebc489f
Add arch attributes display to GUI
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-18 14:13:45 +02:00
Clifford Wolf
a8ca33a33a
Add stringf() helper function
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-18 14:13:27 +02:00
Clifford Wolf
97520bb728
Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr
2018-08-18 13:06:21 +02:00
David Shah
5fe29922fd
ecp5: Speedup router with slightly better estimates
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-18 11:54:53 +02:00
Miodrag Milanovic
3c51007026
do not break if there are no nets loaded from sym section
2018-08-18 10:28:50 +02:00
Eddie Hung
17918b5992
Fix for multiple id_SLICE_LUT6 per actual SLICE
2018-08-17 23:05:12 -07:00
Eddie Hung
d05ac75fda
Add basics for XDL exporter
2018-08-17 21:52:34 -07:00
Miodrag Milanovic
8965922219
Added ability for static builds
2018-08-16 10:32:34 +02:00
ZipCPU
b945de8b1f
JSON-PARSER: Fixed bug in properly reading neg #s
2018-08-15 08:09:55 -04:00
ZipCPU
e93c990f42
Fixed JSON parser: negative values and line numbers
...
1. jsonparse.cc now access negative numbers, properly parsing the sign
2. On any failure to properly parse, a line number is now provided with the
unexpected character error
2018-08-14 18:00:16 -04:00
Eddie Hung
b8b9813056
id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation()
2018-08-14 08:42:27 -07:00
Clifford Wolf
428f0b9eba
Add Arch attrs API
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-14 17:16:14 +02:00
Eddie Hung
72c785db0e
Convert to use torc_info
2018-08-12 22:09:16 -07:00
Eddie Hung
7b15569c69
Use general pin names for QUARTER_SLICE
2018-08-12 20:29:04 -07:00
Eddie Hung
56b7299cca
{SLICEL,SLICEM} -> QUARTER_SLICE
2018-08-12 20:21:03 -07:00
Eddie Hung
f6f20dce0c
Rename ddb to torc
2018-08-12 19:20:13 -07:00
Eddie Hung
8dedd7a83c
Add stub for XDL output
2018-08-12 19:07:33 -07:00
Eddie Hung
13e30a4eb1
Add nextpnr-xc7 to gitignore
2018-08-12 18:56:36 -07:00
Eddie Hung
0fe579f046
Add torc symlink
2018-08-12 18:56:25 -07:00
