Commit Graph

8 Commits

Author SHA1 Message Date
gatecat
377f56c151 interchange: Cope with undriven nets in more places
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-14 10:58:42 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
gatecat
64f5b1d031 interchange: Don't error out on missing cell ports
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
Keith Rothman
c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
Keith Rothman
9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
Keith Rothman
c8dccd3e7b Implement debugging tools for site router.
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:56:11 -07:00
Keith Rothman
91ca5f110b Re-work LUT mapping logic to only put VCC pins when required.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:13 -07:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router.
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:54:49 -07:00