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232 Commits

Author SHA1 Message Date
gatecat
59a29e5f42 nexus: Use a toposort when preplacing clock primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-05-17 06:31:43 +02:00
gatecat
4a4025192a run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-26 09:54:34 +01:00
gatecat
56587859d3 nexus: Improve error reporting for illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-22 15:40:29 +01:00
gatecat
fe52840054 archapi: Add new API for global constant routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
gatecat
a9a9251e42 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-31 10:30:19 +02:00
gatecat
977180524a nexus: More DPHY clock ports that require general routing hop 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-23 11:42:39 +02:00
gatecat
a01e2c9068 nexus: Be robust to parameters shorter than expected 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-23 11:42:39 +02:00
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
rowanG077
cb4846a58d build: push INSTALL_PREFIX from env to cmake var 2023-06-12 14:11:36 +02:00
gatecat
e4fcd3740d cmake: Make HeAP placer always-enabled 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 10:38:11 +01:00
gatecat
61021a22ee nexus: Check IO-bank compatibility 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-21 11:18:35 +01:00
gatecat
7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:20:39 +01:00
David Lattimore
1602774d27 nexus: Transform registered output parameters 
Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
 2022-10-05 14:40:49 +11:00
myrtle
f4e6bbd383
Merge pull request #1019 from antmicro/support-clock-relations 
Support cross-domain clock relations in timing analyser
 2022-09-20 15:55:43 +02:00
gatecat
7ca3ba3835 nexus: Add ES2 device names and --list-devices 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 12:27:36 +02:00
Maciej Kurc
1f1bae3e23 Code cleanup 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-31 16:19:15 +02:00
Maciej Kurc
8b6be09809 Fixed port timing classes of DCC ports in the Nexus architecture 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:13 +02:00
gatecat
c60fb94b6c refactor: Use IdString::in instead of || chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 18:58:22 +01:00
gatecat
f7354d092d nexus: Add timing data for LRAM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 15:47:22 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
ad502bf64b nexus: Fix CSDECODE parsing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-07-19 09:58:00 +01:00
Maciej Dudek
8c4e3e91cc Change write_dcc to work with tilegroups from prjoxide 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-05-27 10:58:39 +02:00
gatecat
2ed68a21db clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-31 10:49:00 +01:00
Maciej Dudek
b9e76d1bcd Rename parse_lattice_param to parse_lattice_param_from_cell 
Add new definition for parse_lattice_param

Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-30 14:59:47 +02:00
Maciej Dudek
49cc4ca30b Nexus: Fixed OSCA parameters, add pll default parameters 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-18 17:26:06 +01:00
gatecat
14d53dfec8 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-17 19:24:05 +00:00
Maciej Kurc
237391c1b8 nexus: Corrected auto frequency constraint for LF output of OSCA 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-16 09:20:15 +01:00
Maciej Kurc
43861c0ee2 nexus: Added support for the DCS Bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-16 09:20:15 +01:00
Maciej Kurc
1cc71c7846 nexus: Added FASM feature emission for DCC and port timing class info 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-15 10:43:31 +01:00
gatecat
df7e26c1aa clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-09 17:12:59 +00:00
Maciej Dudek
191be632e2 nexus: DCCs cannot be cascaded 
This commit solves implicit cascading when clock signal drives DCC and logic

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-09 14:13:29 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
Dan Callaghan
5c30093360 nexus: reduce OSCA worst case to 7% 
The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):

https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780

Older documents listed a wider frequency range but ±7% is the range for
production parts.
 2022-02-10 15:48:06 +11:00
gatecat
5007cd3603
Merge pull request #905 from YosysHQ/gatecat/nexus-disable-dcsroute 
nexus: Hotfix to disable unimplemented DCS routethru
 2022-02-03 21:40:30 +00:00
gatecat
84399caebe run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-03 15:28:46 +00:00
gatecat
d446a29987 nexus: Hotfix to disable unimplemented DCS routethru 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-03 14:59:25 +00:00
Maciej Kurc
3042f9e792 Fixed correction of Nexus OSCA frequency constraints 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-02-02 09:24:28 +01:00
Alessandro Comodi
676e56e5d4 nexus: add option to modify the mult factor of the estimate delay 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-02-01 11:18:17 +01:00
Maciej Kurc
e51e82d6a9 Added honoring OSCA output frequency tolerance during constraints generation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-28 13:51:10 +01:00
Maciej Kurc
18f71ace8c Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE macro 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-25 12:08:52 +01:00
Karol Gugala
500fa6f442 nexus: handle SLEWRATE in pdc 2021-12-20 15:09:03 +01:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
gatecat
a306860144 nexus: router1 speedup based on #867 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-17 15:06:19 +00:00
gatecat
35feb7ebba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:02:39 +00:00
Maciej Kurc
41accf84ce Added checking if all FFs added to an existing cluster have matching configuration 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-23 15:16:26 +01:00