gatecat
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c90d872e35
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xilinx: Filter out another missing pip type
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-26 15:56:20 +02:00 |
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Adrien Prost-Boucle
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437fb70ed3
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Himbaechel xilinx : Fix packing of cascaded DSP
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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9da05b6001
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Himbaechel xilinx : DSP packing : Emit a non-fatal error message
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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2031a067a0
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Himbaechel xilinx : More flexibility about types of DSP parameters
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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81bf92a855
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Himbaechel xilinx : DSP packing : Disable clustering
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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8a0e062520
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Himbaechel xilinx : DSP packing : Improve code efficiency
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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9bea22ed1e
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Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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ad9a54cc69
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Himbaechel xilinx : More cascaded input ports for which routing is skipped
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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04f5f80766
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Himbaechel xilinx : Add safety check in DSP packing for 7-series
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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db0c99199e
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Himbaechel xilinx : Add support of DSP packing for 7-series
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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fa55e93848
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Himbaechel xilinx : Fix regex to parse Zynq device names
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2024-08-19 21:06:45 +01:00 |
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gatecat
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e2a887ef0d
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himbaechel: Switch default back to router1 for now
Signed-off-by: gatecat <gatecat@ds0.me>
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2023-11-17 09:09:59 +01:00 |
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gatecat
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5bfe0dd1b1
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himbaechel: Adding a xilinx uarch for xc7 with prjxray
Signed-off-by: gatecat <gatecat@ds0.me>
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2023-11-14 17:12:09 +01:00 |
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