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Author SHA1 Message Date
gatecat
cb957795a3 Update docs/archapi.md 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 11:25:53 +00:00
gatecat
d83259828e
Merge pull request #587 from YosysHQ/gatecat/generic-vcc 
generic: Don't generate Vcc if not needed
 2021-02-17 11:17:25 +00:00
gatecat
399c24c805 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:45:23 +00:00
gatecat
6b4bd0993f generic: Don't generate Vcc if not needed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:24:06 +00:00
gatecat
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only 
Add Cell -> BEL Pin maps to FPGA interchange arch.
 2021-02-17 10:16:45 +00:00
gatecat
a77ceec5cf
Merge pull request #585 from YosysHQ/gatecat/remove-ivbfc 
Remove isValidBelForCell
 2021-02-17 08:50:31 +00:00
Keith Rothman
26a187e5eb Require --package when arch BBA contains multiple packages. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 14:00:01 -08:00
Keith Rothman
bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps. 
This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 09:37:19 -08:00
gatecat
a74d1a8b32 Bump test submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:35:01 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
815b57b9e1
Merge pull request #583 from litghost/add_fpga_interchange_front_and_backend 
Add FPGA interchange front and backend
 2021-02-16 09:48:40 +00:00
Keith Rothman
1be70320b9 Pull in fix for out of source builds. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
2c7ee44046 Move CMake logic into fpga-interchange-schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
6b04fd1524 Small fixes from review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
e60dda57f3 Add libcapnp-dev for FPGA interchange compilation support. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
664407089b Add FPGA interchange frontend and backend. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
5e11e29ba2 Add interchange schema 3rdparty. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
gatecat
9fc02041fe
Merge pull request #584 from YosysHQ/gatecat/generic-belpin 
Add bel pin mapping control to nextpnr-generic
 2021-02-15 16:19:25 +00:00
gatecat
f0b2a91bda generic: Update docs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-15 10:37:06 +00:00
gatecat
a8a5153873 generic: Add bel pin mapping test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-15 10:22:29 +00:00
gatecat
a002ccfbc1 generic: Add APIs for controlling cell->bel pin mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-15 09:58:56 +00:00
gatecat
065f46daeb
Merge pull request #578 from YosysHQ/machxo2-rebase 
machxo2, rebased and updated
 2021-02-15 09:39:56 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
gatecat
f1ccc0e205
Merge pull request #582 from litghost/add_xdc_parser 
Add XDC parser to FPGA interchange
 2021-02-12 22:40:41 +00:00
Keith Rothman
033cc6731b Add FPGA interchange tests to CI. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 13:48:50 -08:00
Keith Rothman
5312945757 Update tests to include XDC unit test. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
82ab3c1aad Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
8a860857ea Remove capnp and libz for XDC parser PR. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
c96d0f225c Refactor XDC parser into a little class for testing purposes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
d987bd2997 Add unknown handles to convert [0] to "[0]". 
Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0
with zero arguments", rather than just "[0]".  To prevent exposing
non-Tcl users this, "[<number>]" just return themselves.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
a0bd313139 Add FPGA interchange XDC parser. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
gatecat
cede682585
Merge pull request #579 from litghost/add_control_for_split_io 
Add control to whether GenericFrontend splits IO ports.
 2021-02-12 18:22:06 +00:00
Keith Rothman
e28dedbbe3 Update docs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 08:07:09 -08:00
gatecat
9c9a02628d ci: Bump prjtrellis version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 11:51:21 +00:00
gatecat
d3688982ac Fix bad rebase 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 11:16:59 +00:00
gatecat
6de733b38c machxo2: Misc tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:43:15 +00:00
gatecat
33eca9a3d2 machxo2: Python bindings and stub GUI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:40:03 +00:00
gatecat
8f5133d811 machxo2: Use snake_case for non-ArchAPI functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
b539363cd0 machxo2: Use IdStringLists in earnest 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
3f7618283d machxo2: Update with Arch API changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
William D. Jones
32433db7ae machxo2: Prepare README.md for first PR. 2021-02-12 10:36:59 +00:00
William D. Jones
3dbd5b0932 machxo2: Add prefix parameter to simtest.sh. Remove show command from 
simtest.sh. Update README.md.
 2021-02-12 10:36:59 +00:00
William D. Jones
730e543ca6 machxo2: Add prefix parameter to simple.sh. Update README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
0b0faa2f1c machxo2: Fill in more about mitertest.sh in README.md and clean up a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
73c851d8e0 machxo2: Add two new examples: blinky_ext and aforementioned UART. 2021-02-12 10:36:59 +00:00
William D. Jones
74b5e846a5 machxo2: auto-top does not work for smt miter either. 2021-02-12 10:36:59 +00:00
William D. Jones
77bb3e73cd machxo2: Fix unhelpful comment in mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
2b54e87548 machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a38b0536 machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top". 2021-02-12 10:36:59 +00:00
William D. Jones
0aa472fb3a machxo2: Add prefix paramter to demo.sh. 2021-02-12 10:36:59 +00:00