caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
915 Commits 22 Branches 7 Tags 17 MiB
cc6e0e7df3
Commit Graph

915 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Miodrag Milanovic
57c63e6921 create io cells out of asc 2018-07-21 17:54:35 +02:00
Miodrag Milanovic
912a79dc33 add cells that are in default state or no configuration 2018-07-21 17:38:22 +02:00
Miodrag Milanovic
7beb4739d4 Add used cells and attach them to bels 2018-07-21 17:04:47 +02:00
Clifford Wolf
41194d934b Refactoring of router1 
- Use source-sink pairs as jobs, not whole nets
- Route nets with smallest slack first
- Preserve routes for already routed source-sink pairs
- Add small incentive for re-using wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 17:02:53 +02:00
David Shah
80097526ee Fix placement bug with VexRiscV reported by John McMaster 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-21 16:45:46 +02:00
Miodrag Milanovic
13339c0355 Assign proper pips 2018-07-21 15:08:49 +02:00
Miodrag Milanovic
3afcd812c9 add only missing net 2018-07-21 14:41:04 +02:00
Clifford Wolf
a8eadb5ba2 Fix minor issue in GUI Wire properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 13:53:29 +02:00
Clifford Wolf
78f40ca0af Change DelayInfo semantics to what we actually need 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 13:52:59 +02:00
Clifford Wolf
c556242976 Add getWireDelay API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 13:38:44 +02:00
Miodrag Milanovic
09a68affa3 Fix warnings and status 2018-07-21 12:22:41 +02:00
Miodrag Milanovic
fe239366b5 Made save project work as well 2018-07-21 12:15:50 +02:00
Miodrag Milanovic
ec4fc0f830 made open project to work 2018-07-21 11:24:29 +02:00
Miodrag Milanovic
20941292ad fix introduced bug 2018-07-21 09:22:09 +02:00
Sergiusz Bazanski
be14e161ae Re-enable drawing Pips. 2018-07-20 18:35:42 +01:00
Sergiusz Bazanski
0311a27a53 Use UI lock for yielding 2018-07-20 18:34:59 +01:00
Sergiusz Bazanski
5d0dbe9db9 clang-format 2018-07-20 18:24:34 +01:00
Sergiusz Bazanski
76e5236fb3 Nuke IdStringDB 2018-07-20 18:24:16 +01:00
Miodrag Milanovic
9f0be8cd5f make new context work again 2018-07-20 19:16:36 +02:00
Sergiusz Bazanski
b5b956bd21 Remove dead code. 2018-07-20 17:57:16 +01:00
Miodrag Milanovic
34ec70e88b Bind wires to net 2018-07-20 18:42:27 +02:00
David Shah
0d6f6f410d Merge branch 'gridapi' into 'master' 
Gridapi

See merge request SymbioticEDA/nextpnr!11
 2018-07-20 16:27:27 +00:00
Clifford Wolf
fd8239e170 Add Location APIs to generic arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-20 18:09:22 +02:00
Clifford Wolf
f6fa0300ae Improve iCE40 and common Loc code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-20 17:33:57 +02:00
Clifford Wolf
e16b4a325e Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi 2018-07-20 17:13:26 +02:00
Sergiusz Bazanski
19f4b68f07 clang-format and uncomment debug 2018-07-20 13:19:56 +01:00
Sergiusz Bazanski
b4b111a053 Move pthread yield hack into BaseCtx 2018-07-20 13:15:22 +01:00
Miodrag Milanovic
6c835d76f2 Few more checks on parameters and error eol 2018-07-20 14:06:53 +02:00
Miodrag Milanovic
53034959f3 Start adding bitstream reading for ice40 2018-07-20 13:27:21 +02:00
Sergiusz Bazanski
b84a446eef Mix-in Deterministic RNG at Context instead of BaseCtx 2018-07-20 11:04:54 +01:00
Sergiusz Bazanski
55d5f8f248 Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-electric-boogaloo 2018-07-20 10:59:33 +01:00
Sergiusz Bazanski
0385ad1b1c Refactor renderer thread 2018-07-20 10:58:30 +01:00
David Shah
3bad9c26cf ice40: Optimise reset/enable net checking 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-20 11:36:32 +02:00
David Shah
79dc910b40 ice40: Trim DSP inputs that are constant where appropriate 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:32:30 +02:00
David Shah
bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah
6c38df7295 ice40: Adding cell definition for DSPs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 13:22:46 +02:00
David Shah
0cb9ec0757 ice40: Add virtual padin wires for intoscs and GB_IOs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 12:04:35 +02:00
David Shah
d221e90706 Reducing performance cost of asserts 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 11:43:10 +02:00
David Shah
b0d9b994eb ice40: Adding data for extra cell configuration 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 11:14:43 +02:00
Miodrag Milanovic
2df7e130fb Fix click on wire in net section 2018-07-18 18:37:54 +02:00
Miodrag Milanovic
af8b2b83f6 cell and net now can be selected, fixed issue with highlight 2018-07-18 18:06:47 +02:00
Miodrag Milanovic
19828bdf45 added clear action for browsing history 2018-07-18 17:33:04 +02:00
Miodrag Milanovic
3477263431 removed not used and buggy features 2018-07-18 17:18:44 +02:00
David Shah
50bf32665d ecp5: Tidying up examples 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 16:31:55 +02:00
David Shah
c80934f953 ecp5: Add support for pin name constraints using 'LOC' attributes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 16:01:53 +02:00
David Shah
5393841c66 ecp5: Adding PIO data to chipdb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 15:34:22 +02:00
David Shah
08ceb8a059 ice40: Renaming 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:34:32 +02:00
David Shah
ddd94edfe0 ice40: Fixes for inverted clocks 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:01:19 +02:00
Clifford Wolf
acdaec249a Cleanups in iCE40 blinky and picorv32 tests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-18 13:46:00 +02:00
Clifford Wolf
609794f9e6 Add Net/Cell "udata" field 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-18 13:29:58 +02:00