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731 Commits

Author SHA1 Message Date
Miodrag Milanovic
2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic
c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic
16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic
7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic
275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic
401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic
76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic
b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah
349be76d26 ecp5: Add support for flipflops with preload 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 12:20:25 +00:00
Miodrag Milanovic
0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
David Shah
1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:56:04 +00:00
David Shah
ff30bc87fe ecp5: Fix placement of DDRDLLA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:50:13 +00:00
David Shah
b4e9f5c3a6
Merge pull request #356 from YosysHQ/ecp5-ff-density 
ecp5: Improve flipflop packing density
 2019-11-27 11:22:14 +00:00
David Shah
98fe4438f1 ECP5 support is no longer experimental 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 16:10:53 +00:00
David Shah
aee2e01983 ecp5: Improve flipflop packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-20 18:22:22 +00:00
David Shah
08cf545d9b Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr" 
This reverts commit 6a7d1fe53d, reversing
changes made to c3d4117a21.
 2019-11-20 17:10:11 +00:00
David Shah
67e216f8fb ecp5: Add support for promotion of LSRs to global network 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-19 14:08:35 +00:00
David Shah
c3d4117a21 ecp5: Fix handling of custom DEL_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 22:03:11 +00:00
David Shah
36c0ff2dbc ecp5: Fix dynamic DELAYF control 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 20:58:08 +00:00
David Shah
9a848d9d76 ecp5: Add logic utilisation before packing statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 16:54:42 +00:00
David Shah
d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf 
Improve handling of top level IO and add SDF support
 2019-11-18 14:28:40 +00:00
Miodrag Milanovic
da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic
2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic
522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic
6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic
afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic
74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic
43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic
9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic
f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah
21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:27:51 +00:00
David Shah
58b7cb920f ecp5: Fix placement of ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:07:51 +00:00
David Shah
5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 22:21:18 +01:00
David Shah
bac8335222 ecp5: Add constids for new timing cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:50:50 +01:00
David Shah
475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah
36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic
49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic
d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
David Shah
b582ba810c ecp5: Make database build depend on constids.inc 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:29:07 +01:00
Miodrag Milanovic
0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic
847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic
e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eafc0e4e9e Added type to wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah
a22f86f861 ice40: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-19 13:01:00 +01:00
David Shah
cf5cbd1153 ecp5: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-18 15:58:57 +01:00
David Shah
8f86ccc412 ecp5: Add support for ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:52:31 +01:00
David Shah
f2fd1bf80a ecp5: Fix tristate IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:35:16 +01:00
David Shah
c6401413a4 ecp5: Add support for IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:23:35 +01:00
David Shah
a14555c8d1 ecp5: Add IDDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 12:07:56 +01:00
David Shah
21847a55e0 ecp5: Add ODDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 11:23:20 +01:00
David Shah
9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah
cba36239a4 ecp5: Fix parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-04 14:54:31 +01:00
David Shah
d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah
cb71b488ec
Merge pull request #332 from YosysHQ/dave/python-refactor 
Improving Python API and adding docs for it
 2019-09-19 20:15:42 +01:00
David Shah
8351ae275e Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-precompiled-bba 2019-09-19 16:02:10 +01:00
David Shah
f8719a5717
Merge pull request #330 from zeldin/bba 
bba: Default to native endian in bbasm
 2019-09-19 15:57:23 +01:00
Sean Cross
062091e9e4 ecp5: add support for PREGENERATED_BBA_PATH 
Support pre-generated bba files to speed up compiling on Windows
and get it compiling on Darwin.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 11:32:44 +08:00
David Shah
d5e4986e1b python: Refactor out bindings shared between ECP5 and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 16:15:07 +01:00
David Shah
c2299c8972 python: Fix getWireBelPins 
Fixes #327

Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 15:59:16 +01:00
Marcus Comstedt
2f9b04fd56 CMake: Generate chipdbs in build tree when building out-of-tree 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 13:42:17 +02:00
Marcus Comstedt
3d9ce8836c bba: Require explicit endianness flag, and supply it 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 12:30:03 +02:00
David Shah
bc6b47efe0
Merge pull request #329 from YosysHQ/dave/net_aliases 
json: Add support for net aliases
 2019-09-13 19:01:26 +01:00
David Shah
95540763b9 json: Add support for net aliases 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 17:27:15 +01:00
David Shah
2ace9b5ad3 ecp5: Move clock constraints across IO and DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 16:50:07 +01:00
Sean Cross
f98960b936 ecp5: use $PYTHON_EXECUTABLE for python path 
Sometimes the python executable might have a different name.  Cmake
sets the $PYTHON_EXECUTABLE variable to point to the binary path,
so use this variable.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-09 22:10:51 +08:00
David Shah
04be9a71f9 ecp5: Add support for clock gating with DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 10:45:12 +01:00
David Shah
9f9920f92b ecp5: Add full part name to bitstream header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 14:36:20 +01:00
David Shah
78f86ce67a ecp5: Add GSR/SGSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:14:41 +01:00
Arnaud Durand
a26c9bb6d9 Rename clock restriction attribute to "noglobal" 2019-08-24 18:09:42 +02:00
Arnaud Durand
a947f09bfb Restrict clock promotion to global 2019-08-22 00:43:03 +02:00
David Shah
c70f87e4c5
Merge pull request #309 from YosysHQ/dsptiming 
ecp5: Conservative analysis of comb DSP timing
 2019-08-09 10:27:15 +01:00
David Shah
c9969c1593 Add deprecation warning for default packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:35:55 +01:00
David Shah
f0abbc71b5 ecp5: Fix handling of missing ports in LUT permutation 
Fixes #310

Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:24:01 +01:00
David Shah
e55946bec7 clangfromat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:46:53 +01:00
David Shah
661237eb64 ecp5: Add --out-of-context for building hard macros 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:22:47 +01:00
David Shah
7126dacccd ecp5: Add a check for legacy parameter values 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 09:53:33 +01:00
David Shah
ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah
1839a3a770 Major Property improvements for common and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 14:52:15 +01:00
David Shah
d297a96dc1 ecp5: Fix missing LUT inputs, fixes #301 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-10 09:34:22 +01:00
David Shah
2da41a66c7 ecp5: Conservative analysis of comb DSP timing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 15:09:54 +01:00
David Shah
8f2813279c
Merge pull request #284 from YosysHQ/json_write 
Initial support for writing to json files from nextpnr.
 2019-07-03 12:39:38 +01:00
whitequark
1b3c8ea9c1 CMake: serialize chipdb generation by default. 
Fixes #296.
 2019-06-26 21:31:24 +00:00
whitequark
640285755e CMake: formatting. NFC. 2019-06-26 21:27:57 +00:00
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
Miodrag Milanovic
9affcf82d9 default for 5G is speed 8 2019-06-21 18:06:01 +02:00
David Shah
df8688c227 ecp5: Delay tweaking for lower speed grades 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:55:23 +01:00
David Shah
7ae64b9477 ecp5: Reduce cfg.criticalityExponent for now 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:20:46 +01:00
Miodrag Milanovic
66ea9f39f7 enable lading of jsons and setting up context 2019-06-14 15:18:35 +02:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic
ca7e944d7a restore arch info for ecp5 2019-06-14 08:55:11 +02:00
Miodrag Milanovic
03dff10cbd Load properties from json and propagate to context create 2019-06-13 20:42:11 +02:00
Miodrag Milanovic
4de147d9e4 Save settings that we saved in project 2019-06-13 18:39:16 +02:00
Miodrag Milanovic
1cd4a4d17a Remove concept of project and code connected 2019-06-13 17:42:41 +02:00
Miodrag Milanovic
856760599e Use properties for settings and save in json 2019-06-12 18:34:34 +02:00
David Shah
187db92b05 ecp5: Improve error message for bad chars in BRAM init strings 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-08 10:52:37 +01:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
54175f9187 No need for this one 2019-06-07 13:24:16 +02:00
David Shah
15a1d4f582 ecp5: Use an attribute to store is_global 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-07 11:55:20 +01:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Miodrag Milanovic
d5d8213871 Added support for attributes/properties types 2019-06-01 15:52:32 +02:00
Tobias Müller
ea91ea163e Use cmake's find_library to search for pytrellis. 2019-05-11 12:39:50 +02:00
David Shah
12f375a239 ecp5: Fix USRMCLK primitive 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-10 18:51:45 +01:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
David Shah
23f2fff1c8 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:39:05 +00:00
David Shah
fcc3bb1495 ecp5: Speedup cell delay lookups 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
bd12c0a486 HeAP: Add PlacerHeapCfg 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
7142db28a8 HeAP: Make HeAP placer optional 
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
2e2f44c82e HeAP: tidying up 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
8295f997ae HeAP: Use for ECP5 as well as iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
ea56dc9d08 HeAP: Add TAUCS wrapper and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
493d6c3fb9 Add Python helper functions for floorplanning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
0279f63710
Merge pull request #243 from YosysHQ/ecp5lpf 
ecp5: Improve constraint-related error handling
 2019-02-28 15:01:42 +00:00
David Shah
8744c46ea0 ecp5: Fix handling of CRLFs and uppercase frequency units in LPF 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-27 22:54:32 +00:00
David Shah
a2d906a3fd ecp5: Increase ripup penalty 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 18:08:26 +00:00
David Shah
ba4150aecc ecp5: Add an error for mixed constrained/unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 14:45:43 +00:00
David Shah
81b176e150 ecp5: Improve error handling and warning generation in LPF parser 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 14:40:38 +00:00
David Shah
df79d94944 ecp5: DELAY fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
95a85c8ea7 ecp5: Improve packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
a0fa164399 ecp5: Add criticality-based LUT permutation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
f363dd2d3c ecp5: Delay tuning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
4ec2bd1e5d ecp5: Fix global clock routing with multiclock DPRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
55b0b60d9d ecp5: Router performance improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
f5b11ce075 ecp5: Implement budget overrides for carry chains and SLICE muxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
af3ff143be ecp5: Improve delay model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
998d055ea7 ecp5: Speed up timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
64dc453f12 ecp5: DELAYF/G fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 13:53:06 +00:00
David Shah
15314538f8 ecp5: Add list of supported primitives 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
0d83f3fcfe ecp5: Connect unused DQSBUF inputs to GND 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
ab50a6ef54 ecp5: Compute derived constraints iteratively 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
0bc88e622c ecp5: Add support for 'FREQUENCY NET' and 'FREQUENCY PORT' in lpf 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
ae6c1170ef ecp5: Derived constraint support for PLLs, clock dividers and oscillators 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
e50ab2106f ecp5: Fixes for litedram 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
3b50b57f05 ecp5: Add DIFFRESISTOR support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
f960139768 ecp5: Add support for referenced inputs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
817ba5a4b9 ecp5: Add DELAYF/DELAYG support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-24 10:28:25 +01:00
David Shah
fd52db813f ecp5: Add TERMINATION support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
491d64293d ecp5: Add DDRDLLA support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
68abcb365a ecp5: Add ECLKSYNCB support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
49e9453820 ecp5: Add TSHX2DQSA support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
82ad10a395 ecp5: Add TSHX2DQA support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
6e8fbe8cdf ecp5: Add IDDRX2DQA support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
4e49ab1625 ecp5: Add ODDRX2DQSB suppport 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
6f203dfd7b ecp5: Add ODDRX2DQA support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
4402361246 ecp5: Helper functions and bitstream for DQS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
eb45956d0e ecp5: Constraint checker and placer for DQSBUFM 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
fe2375324d ecp5: Add OSHX2A support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
8a64a72a21 ecp5: Add IDDRX2F support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
52d1954d96 ecp5: Packing of ODDRX2F 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
63e1f02c65 ecp5: Helper functions for DQS and ECLK 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
db1666fc3d ecp5: Add timing data for DQS-related cells 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
5cfc7674c1 ecp5: Add DQS groupings to database 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
4c7306185e ecp5: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-14 12:31:33 +00:00
David Shah
9026ab8886
Merge pull request #228 from YosysHQ/ecp5_embed_base 
ecp5: Embed baseconfigs in nextpnr
 2019-02-14 12:20:41 +00:00
Miodrag Milanović
c52202233a
Merge branch 'master' into mmaped_chipdb 2019-02-12 18:53:20 +01:00
David Shah
565d5eed17 ecp5: Fix global routing performance 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 10:56:17 +00:00
Gabriel L. Somlo
1b28bdd121 ecp5: cmake: Search for pytrellis.so in multiple locations 
If a distro-specific "trellis-devel" package is used, the
pytrellis.so library might be located in a dedicated directory,
rather than under TRELLIS_ROOT.

Search for pytrellis.so in a list of directories, then subsequently
use the first match as part of PYTHONPATH.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-02-10 06:42:38 -05:00
Miodrag Milanovic
8b0af0e48d Fix according to comments on PR 2019-02-10 08:33:52 +01:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
David Shah
4b7ec5cecb ecp5: Add --basecfg deprecation warning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-08 13:52:39 +00:00
David Shah
882775acef ecp5: Embed baseconfig 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-08 13:44:15 +00:00
David Shah
c900bcc949 Merge branch 'ecp5func' 2019-02-08 12:57:17 +00:00
David Shah
e929d221f3 ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-08 12:34:22 +00:00
David Shah
b8bff6b8b5
Merge pull request #210 from twam/master 
Search for trellis in /usr/local/share/trellis if not specified with …
 2019-01-27 14:56:42 +00:00
Miodrag Milanovic
dbaae51159 Make cross compile possible for mingw 2019-01-27 10:10:37 +01:00
Tobias Müller
95ed84fd91 Search for trellis in /usr/local/share/trellis if not specified with -DTRELLIS_ROOT 2019-01-13 17:15:28 +01:00
David Shah
747380537f ecp5: Add PULLMODE support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-07 14:27:58 +00:00
David Shah
1661350d25 ecp5: Check for incorrect use of TRELLIS_IO 'B' pin 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-25 19:45:10 +00:00
David Shah
e76479f379 ecp5: Fix tristate IO insertion 
Fixes #191

Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-22 10:11:18 +00:00
David Shah
dc10fe0319 ecp5: Fix ODDR when used with manually instantiated TRELLIS_IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-19 10:11:29 +00:00
David Shah
d75075e15c ecp5: Fix IOLOGIC ports at the same constant value 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-15 13:52:18 +00:00
David Shah
c01bb88509 ecp5: Add IOLOGIC timing and bitstream; ODDR working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-14 16:40:38 +00:00
David Shah
9dc845b20d ecp5: Add ODDR packing 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-14 14:59:14 +00:00
David Shah
36b1650df7 ecp5: Adding IOLOGIC packing 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-14 09:55:04 +00:00
David Shah
b12a8c1a30 ecp5: Add {S}IOLOGIC constids and cell 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 19:08:48 +00:00
David Shah
dc549cd56b
Merge pull request #159 from YosysHQ/ecp5_pllplace 
ecp5: Pre-place PLLs and use dedicated routes into globals
 2018-12-01 09:14:34 +00:00
David Shah
5ddf99cf5d ecp5: Pre-place PLLs and use dedicated routes into globals 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-30 16:09:56 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
5a1190ade2 ecp5: Fix UR PLL tile coordinates 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 15:35:55 +00:00
David Shah
bbeab72ad9
Merge pull request #143 from daveshah1/ecp5_muxes 
ecp5: Adding support for LUT extension muxes up to LUT7
 2018-11-26 09:37:18 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah
76f575fb29 ecp5: Add support for LUT7 mux 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-18 17:17:46 +00:00
David Shah
458aa20161 ecp5: More optimal LUT6 placement 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 17:36:34 +00:00
David Shah
3ae8b86003 ecp5: Adding mux support up to LUT6 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 17:27:23 +00:00
David Shah
94dc54f4fa ecp5: Add 10% safety margin to pip delays 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:35:01 +00:00
David Shah
1ae722272a ecp5: clangformat timing changes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:27:03 +00:00
David Shah
50b85da619 ecp5: Use speed-grade-specific delay estimate 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
13244e513b ecp5: Fix db import, improve timing data debugging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
19cc284b8c ecp5: Allow selection of device speed grade 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
ffe1166e33 ecp5: Post-rebase fix 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
2024346f4d ecp5: Consider fanout when calculating pip delays 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
cc746d888b ecp5: Fix timing pip classes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
3ecd440748 ecp5: Use new timing data 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
703ff2818f ecp5: Fix timing data import 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
18813f2056 ecp5: Adding real timing data to database 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
David Shah
cfaa6c0e5d
Merge pull request #119 from cr1901/win-fix 
nextpnr-ecp5 Windows Fixes
 2018-11-16 10:00:13 +00:00
David Shah
f07bd98d59 ecp5: Better use of Boost 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 09:58:18 +00:00
David Shah
7e1df82462 ecp5: Regression fix & format 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:54:28 +00:00
David Shah
91a0927196 ecp5: Support LOC attribute on DCUs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
01e0da16f0 ecp5: Add DCU availability check 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
02736d0680 ecp5: Add timing info for SERDES 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
084f9cf63f ecp5: DCU clocking fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
0eba7d9789 ecp5: EXTREFB fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
bc022173f0 ecp5: clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
36178a5713 ecp5: Trim IO connected to top level ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
e9fe444dc7 ecp5: Adding ancillary DCU bels 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
37cbabecfb ecp5: remove debug and clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
c9d83ec08b dcu: Fix bitstream param handling 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
4f8dfd8e1b ecp5: Prefer DCCs with dedicated routing when placing DCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
c5a3571a06 ecp5: Working on DCU 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
983903887d ecp5: DCU bitstream gen handling 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
cc9fb1497d ecp5: Groundwork for DCU support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
David Shah
959d163ba7 ecp5: Improve delay estimates 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-13 14:27:23 +00:00
Pedro Vanzella
710ea1b265 Mark getArchOptions as override in derived classes 2018-11-13 11:03:48 -02:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
d3ad522bfe ecp5: Copy clock constraints during global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
11579a1046 ecp5: EBR clocking fix 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
8af86ff37d ecp5: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
David Shah
9e5aded5c6 ecp5: Fix 85k PLL_LR 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-11 15:12:27 +00:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Miodrag Milanovic
0ad5197ff4 show 4th tresllis_io in tile bounds 2018-11-11 08:25:54 +01:00
William D. Jones
14ad19e064 Use native PATH environment-variable separator on Windows for PYTHONPATH. Fixes 'Bad address' error in cmake. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2018-11-03 13:12:37 -04:00
William D. Jones
553c611936 Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided io.h. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2018-11-03 13:11:01 -04:00
David Shah
04f9b87101 ecp5: Allow setting IO SLEWRATE 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-01 20:41:51 +00:00
David Shah
e005cc6754 ecp5: Add PLL support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 19:52:41 +00:00
David Shah
24a2feda30 ecp5: Separate global promotion and routing 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 16:22:34 +00:00
David Shah
c782f07b1b ecp5: Add IO buffer insertion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 11:30:09 +00:00
David Shah
db0646be8a ecp5: Adding LPF parser 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 10:48:54 +00:00
David Shah
0ac48c6a08 ecp5: DSP fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 16:18:29 +01:00
David Shah
535a6f625a ecp5: Working on DSPs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 11:19:59 +01:00
David Shah
1a06f4b2bd ecp5: Adding DSP support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 20:07:18 +01:00
David Shah
b5faa7ad10 ecp5: Implement ECP5 equivalent of c9059fc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 17:15:34 +01:00
David Shah
1cde208090 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 14:37:58 +01:00
David Shah
8aac6db44b ecp5: Add support for correct tile naming in all variants 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 14:37:24 +01:00
David Shah
3aa3f5d796 ecp5: Add DP16KD timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 13:30:23 +01:00
David Shah
1fc2318c53 ecp5: Optimise DCC placement 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-14 13:22:47 +01:00
David Shah
bda94aa5a5 ecp5: Fix BRAM tile names 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-11 11:51:17 +01:00
David Shah
848ce6d41c ecp5: Fixing BRAM initialisation 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:21:37 +01:00
David Shah
f7466110a5 ecp5: Working on BRAM initialisation 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 13:13:16 +01:00
David Shah
d716292e3d ecp5: BRAM improvements with constant/inverted inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-06 15:59:22 +01:00
David Shah
cd688a2784 ecp5: Fixing EBR constant tie-offs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 16:47:03 +01:00
David Shah
85a95ec250 ecp5: Bitstream gen for DP16KD BRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 15:53:41 +01:00
David Shah
56ab547aeb ecp5: Infrastructure for BRAM bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 14:36:16 +01:00
David Shah
19f828c91c ecp5: Dummy timing entry for BRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:37 +01:00
David Shah
48f08e6d39 ecp5: Adding constids for blockram 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 10:54:30 +01:00
David Shah
bf7161d2b4 ecp5: Negative clock support, general slice improvements 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-02 15:50:45 +01:00
David Shah
8cbc92b7f3 ecp5: Small DRAM routing fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:45:14 +01:00
David Shah
9ebec3b87f clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:20:14 +01:00
David Shah
fd4498736e ecp5: Fix packing of FFs into carry/DRAM slices 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:19:56 +01:00
David Shah
2c96d4770d ecp5: Fix DRAM initialisation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:15:11 +01:00
David Shah
3dfc5b864a ecp5: Remove broken DRAM timing arc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 17:51:36 +01:00
David Shah
c8a9bb807c ecp5: Debugging DRAM packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 17:45:35 +01:00
David Shah
9518c5d762 ecp5: Working on DRAM packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 17:05:02 +01:00
David Shah
885fae8236 ecp5: Handling of DRAM initialisation and wiring 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 16:43:22 +01:00
David Shah
d770eb672f ecp5: Helper functions for distributed RAM support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 15:23:12 +01:00
David Shah
931c78b1bb ecp5: Improve handling of constant CCU2C inputs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 14:42:19 +01:00
David Shah
e7c8818424 ecp5: Fix carry feed out 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 19:27:06 +01:00
David Shah
6a1b49c311 ecp5: Improve mixed no-FF/FF placement 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 18:39:53 +01:00
David Shah
3e399c9f20 ecp5: Carry packing fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 18:10:20 +01:00
David Shah
9218d2e56b ecp5: Relative placement and bitstream gen for carries 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 17:42:47 +01:00
David Shah
fef29d8762 ecp5: First stages of carry packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 17:18:30 +01:00
David Shah
e81a95cf7e ecp5: Add ccu2c_to_slice 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 17:06:06 +01:00
David Shah
2628344298 ecp5: Support code for carry chain handling 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:58:02 +01:00
David Shah
a27c7b45de Refactor chain finder to its own file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:29:26 +01:00
David Shah
6afc2c75fd ecp5: Adding carry helper functions 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:31 +01:00
David Shah
0e0ad26f07 ecp5: Use ArchNetInfo to mark global nets to ignore 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 19:31:49 +01:00
David Shah
ab063b2456 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 18:37:17 +01:00
David Shah
11cdc197bc ecp5: Fix global buffer connectivity and timing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 18:29:23 +01:00
David Shah
f46f205782 ecp5: Fix handling of global to fabric connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 18:06:08 +01:00
David Shah
5e46d1eb98 ecp5: Remove excessive debugging from global promoter 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:38:39 +01:00
David Shah
c5f9a12bb1 ecp5: Global router produces a working bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:36:08 +01:00
David Shah
c2a062d254 ecp5: Fixing global to global user routing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:13:50 +01:00
David Shah
9ff5d5a735 ecp5: Fixing global router bugs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:01:19 +01:00