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210 Commits

Author SHA1 Message Date
gatecat
9b51c6e337 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 14:51:33 +02:00
gatecat
a29a17f8f2 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-18 13:54:12 +02:00
gatecat
3e1e783873 himbaechel: Initial timing support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-08 09:55:49 +02:00
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
gatecat
b0a78de78f fabulous: Support for configurable LUT size 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-13 13:29:52 +02:00
gatecat
6455b5dd26 viaduct: Add support for GUIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-11 19:11:54 +02:00
gatecat
23f2877dde fabulous: Fix bel names for pass bels in v2 format 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-05 15:45:18 +02:00
gatecat
e4fcd3740d cmake: Make HeAP placer always-enabled 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 10:38:11 +01:00
gatecat
2f509734df fabulous: Misc improvements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-28 21:39:25 +01:00
gatecat
cdd7bb676f fabulous: Support for complex flops in PnR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-28 21:39:25 +01:00
gatecat
5d0aa77861 fabulous: Add timing model for carries 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 08:42:56 +01:00
gatecat
26fcf349ad fabulous: LUT permutation support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 08:42:56 +01:00
gatecat
14050f991b fabulous: Global constant wires scheme 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-23 10:05:55 +01:00
gatecat
0ed964247e fabulous: Add support for packing carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-21 14:41:48 +01:00
gatecat
16bcc51ffb fabulous: Further tweak magic numbers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 15:53:15 +01:00
gatecat
06b675b345 fabulous: Add fake timings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 11:56:58 +01:00
gatecat
eb70e95079 fabulous: Improve names for BRAM bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-10 13:23:31 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
gatecat
3a61bb4119 viaduct: Fix constant connectivity 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-06 10:04:59 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:20:39 +01:00
gatecat
6930ab3acd fabulous: Tweak delay estimate 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-10 10:55:37 +01:00
gatecat
3826a31ad3 fabulous: Pack, validity check and FASM support for muxes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 13:27:51 +02:00
gatecat
124c0fc812 fabulous: Add split MUX bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 12:03:16 +02:00
gatecat
376cedd558 fabulous: fix, but disable, IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-16 09:32:15 +02:00
gatecat
f423055390 fabulous: Add a viaduct uarch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-09 14:48:57 +02:00
gatecat
47da562600 viaduct: Allow passing command line options to uarch with -o 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-15 12:15:00 +02:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
37f0886cb9 generic: addBelPin with direction as an arg 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-04 10:55:19 +02:00
gatecat
09e388f453 netlist: Add PseudoCell API 
When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.

The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
 2022-07-08 14:30:57 +02:00
gatecat
e1ba379fb7 generic: Use arch_pybindings_shared 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-07-04 18:39:00 +02:00
gatecat
f0d4e4fbc3 generic: Add some extra helpers for viaduct uarches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-02 11:02:09 +01:00
gatecat
20cfafa109 generic: Add missing uarch guard 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-27 14:18:42 +01:00
gatecat
c4e47ba1a8 generic: Allow bel pins without wires 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-04 19:49:44 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
Lofty
fbb02e2860 okami: new Viaduct arch 2022-02-24 20:38:56 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
e5bfff6e9f viaduct: Allow constraining only cascades without fanout 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-04 20:49:32 +00:00
gatecat
5ef5c33e9e generic: Add missing Pip vector binding 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-04 15:54:41 +00:00
gatecat
e88bd34c02 Viaduct API for a hybrid between generic and full-custom arch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-04 20:19:29 +00:00
gatecat
59874188a6 generic: Refactor for faster performance 
This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-30 11:54:08 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:17:55 -07:00