David Shah
6da8f98eac
ice40: Lock out mutually exclusive pips
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-06-10 12:17:55 +02:00
David Shah
d0431225f1
ice40: Writing an empty ASC file
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-06-10 11:56:07 +02:00
David Shah
89d5280bf6
ice40: Adding non-routing config bits to database
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-06-10 11:14:50 +02:00
David Shah
48b72126c9
ice40: Add switch data to database
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-06-10 10:54:55 +02:00
Clifford Wolf
8cabb39d6d
Getting rid of .nil() methods, compare with zero- and default-constructed objects instead
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-09 18:41:38 +02:00
Clifford Wolf
dfbfbf87db
Add very basic router
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-09 18:19:20 +02:00
ZipCPU
4499864024
Applied clang-format to my own contributions
2018-06-07 15:38:24 -04:00
ZipCPU
c13c15bada
Set the default log to stdout
2018-06-07 09:52:32 -04:00
ZipCPU
f32b9622d5
Initial (random) placer capability
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This commit also includes changes to jsonparse to allow it to
1) recognize ports with no connection, and set their net pointers to NULL
2) recognize designs with a ports node rather than a ports_direction
The rule checker has also been modified to accommodate possible NULL netlists
The ice40 chip now also has iterator operations ++bi and bi++.
2018-06-07 09:38:14 -04:00
David Shah
547d4fe3ee
ice40: Refactor PortPin and add Python binding
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-06-07 14:36:35 +02:00
Clifford Wolf
1ea8fa4881
clang-format for design and chip codebase
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-07 12:56:49 +02:00
Clifford Wolf
72b4bba0e7
Add ice40 geometry information
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-06 16:42:42 +02:00
Clifford Wolf
f07682f515
Add ice40 --test mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-06 16:01:31 +02:00
Clifford Wolf
5ff9aafb20
Refactor Chip API and iCE40 database
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-06 15:13:41 +02:00
Clifford Wolf
d13a84b687
Add iCE40 blockram bels
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-04 12:37:56 +02:00
Clifford Wolf
eb3c89bee9
Replace GuiLine with GraphicElement
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-04 12:02:58 +02:00
Clifford Wolf
6840ffd9c0
Add iCE40 SB_IO bels
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-03 16:16:59 +02:00
Clifford Wolf
20d7cd0194
Add ice40 ICESTORM_LC bels
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-02 15:00:33 +02:00
Clifford Wolf
cdb31fdafc
Use singular in type names (BelRange, WireIterator)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-02 12:57:19 +02:00
Clifford Wolf
3b0d1beabb
Add DelayInfo struct
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-29 20:04:29 +02:00
Clifford Wolf
d56e29c47e
Progress in chip.h API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-26 16:08:20 +02:00
Clifford Wolf
757786f134
Progress in ice40 chipdb
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-26 14:56:30 +02:00
Clifford Wolf
1899833b4d
Start work on iCE40 chipdb
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-26 14:27:28 +02:00
