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253 Commits

Author SHA1 Message Date
gatecat
377f56c151 interchange: Cope with undriven nets in more places 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-14 10:58:42 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
Alessandro Comodi
b65dbd5c9e interchange: clusters: always get cell bel map and add asserts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
64b45848d7 interchange: run clang formatter 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
d72c10cb6c interchange: clusters: adjust comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
e8191dc061 interchange: increase chipinfo version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
490ca794c5 interchange: tests: counter: emit carries for xc7 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
104536b7aa interchange: add support for generating BEL clusters 
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Tomasz Michalak
3cc58b3918 fpga_interchange: Add site router tests 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:30 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0426ba4e87 interchange: Add LIFCL-40 EVN tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 09:52:40 +01:00
gatecat
bae83857a3 interchange: Add macro parameter mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
64f5b1d031 interchange: Don't error out on missing cell ports 
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
a146dbdb03 interchange: Add LUTRAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
2759480cb5 interchange: Preliminary implementation of macro expansion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
237b27e50b interchange: Add macro param map rules to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
012b60c9ca interchange: Add macro data to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
Alessandro Comodi
84359f39c5 interchange: phys: add site instance idstr for pseudo tile PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-19 18:48:54 +02:00
gatecat
5a41d2070c Run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-16 16:25:05 +01:00
Alessandro Comodi
428b56570d interchange: pseudo pips: fix illegal tile pseudo PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-14 12:17:53 +02:00
Alessandro Comodi
8c468acff8 interchange: site router: add valid pips list to check during routing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-13 11:00:42 +02:00
Alessandro Comodi
fd93697a2d interchange: arch: do not allow site pips within sites 
During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.

This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-12 18:28:22 +02:00
gatecat
7a1a95a2d6 interchange: Fix bounding box computation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-11 13:02:23 +01:00
Alessandro Comodi
45618faf36 interchange: site router: fix log messages 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-10 14:20:54 +02:00
Alessandro Comodi
beff2b912c interchange: site router: fix illegal site thru paths 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-10 14:05:46 +02:00
gatecat
9a1cad85fe interchange: Adding a basic global buffer placer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:28:59 +01:00
gatecat
9b3fb00908 interchange: Initial global routing implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:28:56 +01:00
gatecat
b8c8200683 interchange: Add more global cell info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:25:18 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
gatecat
49caad0b7b interchange/nexus: Add counter example 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 14:15:37 +01:00
gatecat
dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat
ecf24201ec interchange: Add wire types to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:14 +01:00
gatecat
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword 
interchange: allow LOC keyword in XDC files
 2021-04-20 14:12:14 +01:00
Jan Kowalewski
d1548ed317 interchange: allow LOC keyword in XDC files 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-04-20 14:35:15 +02:00
gatecat
18459a9e4c interchange: Handle disconnected/missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:46:35 +01:00
gatecat
872b3aa63d interchange: Add default cell connections to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:16:26 +01:00
gatecat
d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi
dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat
fc15105643 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:26:39 +01:00
gatecat
93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties 
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.

This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 10:26:32 +01:00
Keith Rothman
ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
3200026e1f [interchange] Remove requirement to have wire_lut. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
8773c645ca [interchange] Prevent site router from generating incorrect LUTs. 
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal.  This case is now prevented by tying the
output of the LUT to an unused net.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c11ad31393 [interchange] Scale edge cost of pseudo pips. 
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h 
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
90aa1d3b7e [interchange] Disallow site edges during general routing. 
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
0d41fff3a7 [interchange] Add crude pseudo pip model. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
gatecat
ff449ca997
Merge pull request #661 from litghost/document_site_router 
[interchange] Add some documentation for the site router.
 2021-04-06 09:20:03 +01:00
gatecat
8e0d8df791
Merge pull request #657 from acomodi/interchange-counter-multi-board 
interchange: counter: testing on multiple boards
 2021-04-06 08:12:02 +01:00
Keith Rothman
4301e4705b [interchange] Add some documentation for the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-05 15:15:48 -07:00
Keith Rothman
009d3b64b6 [interchange] Update to v6 of FPGA interchange chipdb. 
Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:24:06 -07:00
Alessandro Comodi
366f8782cb interchange: counter: testing on multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-01 10:23:07 +02:00
gatecat
ec98fee1ee
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake 
fpga_interchange: Add CMake support for Nexus/prjoxide
 2021-03-31 15:14:51 +01:00
gatecat
3678eff5dc interchange: Fix nexus cmake review comments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-31 10:11:09 +01:00
Keith Rothman
8675945b26 Fix bug where DedicateInterconnect incorrectly allows some placement. 
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 13:24:39 -07:00
Keith Rothman
7e47af1085 [interchange] Fix site pip check for drivers. 
Previous code allowed router to entire sites with no sinks.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 10:04:18 -07:00
gatecat
a003aae7c2 interchange: Split xc7 and nexus chipdb cmake 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
ecfaae7f9e interchange: Add Nexus LUT test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
b6b8959397 interchange: Add Nexus to CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
3cb5e81d50 interchange: Add CMake support for Nexus/prjoxide 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 15:28:19 +01:00
gatecat
692d7dc26d
Merge pull request #645 from litghost/add_counter_and_ram 
FPGA interchange: Add counter and ram tests
 2021-03-29 18:23:16 +01:00
Alessandro Comodi
b5ba3ee9ee interchange: add archcheck tests to all-device-test target 
This increases parallelism and should make the FPGA interchange CI
faster

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
Keith Rothman
f33d02dca9 Update README with latest develpment progress. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:15 -07:00
Keith Rothman
55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove. 
This resulted in valid site routing solutions being missed.  Underlying
bug was an off-by-one error when unwinding a failed solution.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:14 -07:00
Keith Rothman
c8dccd3e7b Implement debugging tools for site router. 
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:11 -07:00
Keith Rothman
cc4f2b4516 Add some FIXME's around VCC assumption in LUT logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
bbe1881293 Add targets to generate YAML outputs for DeviceResource files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
91ca5f110b Re-work LUT mapping logic to only put VCC pins when required. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
5dda3a14ff Fixup some of the re-mapping logic. 
- Add IDEMPOTENT_CHECK define to perform some expected idempotent
   operations more than once to verify they work as expected.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:09 -07:00
Keith Rothman
5e96740451 [FPGA interchange] Small fix to get_net_type. 
If get_net_type was called before the driver was placed, it could return
the wrong value.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
Keith Rothman
22fb2c1548 Enable counter tests and add RAM tests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
Alessandro Comodi
9f28fa4e75 gh-actions: interchange: multiple jobs, one for each device 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:03 +01:00
Alessandro Comodi
1a774a0526 interchange: examples: remove unused makefiles 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:02 +01:00
Alessandro Comodi
b6d2a59fc2 interchange: devices: bel_bucket_seeds -> device_config 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:06:01 +01:00
Alessandro Comodi
15e945aa1c interchange: added boards and group testing across multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:05:58 +01:00
Alessandro Comodi
4812092cdb fpga_interchange: add test data for new architectures 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
658dadaa70 fpga_interchange: use higher java heap space 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
336d31cbcf fpga_interchange: add more devices 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
gatecat
3cc50a5744
Merge pull request #644 from litghost/add_global_buffers 
[FPGA interchange] Add support for global buffers from chipdb.
 2021-03-23 17:33:55 +00:00
gatecat
323da87dec
Merge pull request #643 from litghost/id_constants 
[FPGA interchange] Convert some string constants to IdString.
 2021-03-23 17:33:40 +00:00
gatecat
2300d81c3c
Merge pull request #640 from litghost/inversion_logic 
Initial inverter logic for FPGA interchange
 2021-03-23 16:59:35 +00:00
gatecat
8c85e648df
Merge pull request #639 from litghost/parameter_iteration 
Update parameter processing based on new DeviceResources metadata
 2021-03-23 16:51:28 +00:00
Keith Rothman
720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:41:45 -07:00
Keith Rothman
0dd93035e4 [FPGA interchange] Convert some string constants to IdString. 
Also add some optional diagnostic prints for cell -> BEL pin mapping.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:38:37 -07:00
gatecat
b7bf2c706f
Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin 
interchange: Add nice error for missing cell pins
 2021-03-23 16:34:10 +00:00
Keith Rothman
831b94cdac Initial version of inverter logic. 
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:03:07 -07:00
Keith Rothman
ae71206e1f Update FPGA interchange chipdb to v4 with inverter data. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:45 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
Keith Rothman
af1fba9f52 Update latest version of FPGA interchange schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:00:58 -07:00
gatecat
79400756f5 interchange: Add nice error for missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-23 15:40:34 +00:00