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4,806 Commits 22 Branches 7 Tags 17 MiB
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54 Commits

Author SHA1 Message Date
gatecat
9b51c6e337 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 14:51:33 +02:00
Miodrag Milanovic
95e7598cc6 Fix timing lookup for DP8KC 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
e4cb7ea337 proper clock calc due after funcion change 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
c2b75b355f use timing data 2023-10-02 14:49:17 +02:00
gatecat
a9a9251e42 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-31 10:30:19 +02:00
Miodrag Milanovic
688f1ba983 widelut support for xo2/xo3/xo3d 2023-08-29 10:04:58 +02:00
Miodrag Milanovic
053d89570f Use type name directly 2023-08-17 11:18:45 +02:00
Miodrag Milanovic
83f65169a3 different oscilator for XO3D 2023-08-17 11:18:45 +02:00
gatecat
e3529d3356 machxo2: Global placement and clock routing from nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-08 10:38:16 +02:00
Miodrag Milanovic
91771895b6 Removed not tested/used code 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
10595726c1 fix warning 2023-05-04 14:23:08 +02:00
gatecat
655aee1f9d Fix invalid accesses during certain IO packing cases 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
582cd526ac display freq with two digits after decimal point 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
909917cb61 Add clock constraints for new primitives 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
90a6578c53 handle VLO and VHI 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a2d08dc79e Made PDPW8KC to work 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
8c19e6f83a clangformat 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7ac3d0d901 basic support for few small primitives 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
c6f1f124f2 removed commented and not used code 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
8c38e7ba61 Working BRAM 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
19176ab597 Made PLL to work 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a0ba9afcba CCU2D is auto tied low 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
aacb36bf15 Use CCU2D cell 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
153144022f More of making it inline 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ca3d32e5ac make source more inline with ecp5 2023-05-04 14:23:08 +02:00
Lofty
235a575267 port ecp5 split slice to machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
0ce72e1a31 Use TRELLIS primitives 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
7ad9914e51 Extend chipdb with metadata 2023-03-16 13:37:23 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
William D. Jones
064b6d808e clangformat. 2021-12-16 17:09:29 -05:00
William D. Jones
365a871908 machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports. 2021-12-16 16:59:38 -05:00
William D. Jones
41d09f7187 machxo2: Fix packing for directly-connected DFFs. 2021-07-01 09:59:53 -04:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
3f7618283d machxo2: Update with Arch API changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
William D. Jones
4948e8d914 machxo2: Fix packing when FF is driven by a constant; UART test core working on silicon, fails post-synth sim. 2021-02-12 10:36:59 +00:00
William D. Jones
086bca18b8 machxo2: Add packing logic to handle FFs fed with constant value; UART test core routes. 2021-02-12 10:36:59 +00:00
William D. Jones
3ab300a28e machxo2: Add additional packing phase to pack remaining FFs. 2021-02-12 10:36:59 +00:00
William D. Jones
0250aaaddd machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
695fb7e569 machxo2: Add/fix copyright banners. 2021-02-12 10:36:59 +00:00
William D. Jones
31ea8f8719 machxo2: Use attrmvcp in yosys to implement LOC constraint and only check for LOC on FACADE_IO. 2021-02-12 10:36:59 +00:00
William D. Jones
9c37aef499 machxo2: Detect LOC attributes during packing to implement rudimentary user constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
0e63178fe1 machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a3a91b72 machxo2: Clean up packing pass a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
da6204442f machxo2: Add LUT and FF packing functions. 2021-02-12 10:36:59 +00:00
William D. Jones
f2a240550e machxo2: Always remove nextpnr_iobufs for now- assume manually instantiated primitives. 2021-02-12 10:36:59 +00:00