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3,498 Commits 22 Branches 7 Tags 17 MiB
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Author SHA1 Message Date
gatecat
d39e67da7e mistral: First pass at carry packing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
7574eab2b6 mistral: FF validity checking fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
18e05ec852 mistral: Fix constant trimming 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
bacba274a2 mistral: Write LUT inits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
d1f635242d mistral: Add some IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
dea4c6f53f mistral: Setting some more boilerplate bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
27eb3be7da mistral: Add stub RBF generation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
ad5e5f80ca mistral: Rename clock buffer primitive 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
a581526528 mistral: Python and GUI stub 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
386b5b901c mistral: Implement some misc. things 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
c5d983066d mistral: Some preps for generating bitstreams 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
2612853238 mistral: Adding a function for computing ALM LUT masks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
5d191f8297 mistral: Add IO packing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
96f16c8635 mistral: Add a basic QSF parser 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
595b354184 mistral: Add some packing logic based on nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
3fc5396063 mistral: Working on FF validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
1b729d90d0 mistral: Add the 'pin style' stuff based on Nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
d38ff14264 mistral: Working on ALM input assignment 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
e5e2f7bc62 mistral: Add stub pack/place/route functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
879ac39e53 mistral: Renamed arch from cyclonev 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
2938682295 cyclonev: Rebase update 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
9eb0bc482e cyclonev: More validity checking thoughts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
a6ea72fd84 cyclonev: Add validity check and IO bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
fbdcfa9c42 cyclonev: First (untested) pass at ALM validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
1cd22b81da cyclonev: More preparations for validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
9bd7ef5f5f cyclonev: Preparations for validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
24af19b58d cyclonev: Fix some archcheck fails 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
431c4cec9f cyclonev: Rework bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
86ce6abf6a cyclonev: Outline LAB structure 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
c671961c18 cyclonev: Outline functions for creating bels/wires/pips 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b1d3eb07c3 archcheck: Use old connectivity check for CycloneV 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
8677d59b92 cyclonev: Add routing graph 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
5d1b8bf744 cyclonev: Add names and archcheck fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
af0bffbae9 cyclonev: Add some range types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
c3cb9aa3f6 cyclonev: Add enough stubs that it links 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
9901a5fafc cyclonev: Add wire and pip types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
7e57196cf9 cyclonev: Add some useful constids 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
0533818cee cyclonev: Update in line with nextpnr changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
Dan Ravensloft
9f2cbe1762 build bel list in constructor 2021-05-15 14:54:33 +01:00
Dan Ravensloft
170d6cffdd current progress 2021-05-15 14:54:33 +01:00
Dan Ravensloft
fcdf1e0bfd bind/unbind bel 2021-05-15 14:54:33 +01:00
Dan Ravensloft
189164e7c8 Resolve feedback 2021-05-15 14:54:33 +01:00
Dan Ravensloft
b8f58d558c couple of functions implemented 2021-05-15 14:54:31 +01:00
Dan Ravensloft
6ffbb9ed87 cyclonev: basic platform 2021-05-15 14:52:19 +01:00
gatecat
1b5767928d
Merge pull request #706 from acomodi/fix-illegal-site-thru 
interchange: pseudo pips: fix illegal tile pseudo PIPs
 2021-05-14 12:34:32 +01:00
Alessandro Comodi
428b56570d interchange: pseudo pips: fix illegal tile pseudo PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-14 12:17:53 +02:00
gatecat
21d594a150
Merge pull request #700 from acomodi/fix-illegal-site-thru 
interchange: arch: do not allow site pips within sites
 2021-05-13 11:02:15 +01:00
Alessandro Comodi
8c468acff8 interchange: site router: add valid pips list to check during routing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-13 11:00:42 +02:00
Alessandro Comodi
fd93697a2d interchange: arch: do not allow site pips within sites 
During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.

This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-12 18:28:22 +02:00
gatecat
ced31aa917
Merge pull request #704 from YosysHQ/router2_stats 
router2: Add some boundness statistics
 2021-05-12 14:11:14 +01:00