Commit Graph

4284 Commits

Author SHA1 Message Date
Arjen Roodselaar
d5299f144f Add --no-placer-timeout flag to override timeout during refinement 2022-12-19 22:58:52 -08:00
Arjen Roodselaar
2712cbf6e4 Increase timeout 2022-12-19 14:00:19 -08:00
Arjen Roodselaar
6e0311efca Timeout when legal placement can't be found for cell 2022-12-17 16:07:57 -08:00
myrtle
78926b31db
Merge pull request #1064 from YosysHQ/gatecat/ecp5-main-fix
ecp5: Only write bitstream if --textcfg passed
2022-12-17 12:22:36 +00:00
gatecat
bc18d18a95 ecp5: Only write bitstream if --textcfg passed
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-17 10:37:15 +00:00
myrtle
16ffd02a9d
Merge pull request #1061 from yrabbit/fix-clock-gui
gowin: not crush on unknown clock tap's sources
2022-12-14 08:00:02 +01:00
YRabbit
bc3d9f3108 gowin: not crush on unknown clock tap's sources
As preparation for possible changes to the clock wiring system.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-12-14 15:35:55 +10:00
myrtle
b5d30c7387
Merge pull request #1060 from yrabbit/pll-inputs
gowin: BUGFIX: Correctly handle resets
2022-12-09 09:27:58 +01:00
YRabbit
aa8359c73e gowin: BUGFIX: Correctly handle resets
When a single primitive occupies several cells, care must be taken when
manipulating the parameters of that primitive: when creating cells, each
cell must receive a copy of all the parameters and not modify them
unnecessarily.  That is, if possible, it is better to make all parameter
changes before dividing the primitive into cells.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-12-09 12:55:22 +10:00
myrtle
0eb53d59d8
Merge pull request #1059 from YosysHQ/gatecat/validity-errors
Add new option for verbose validity errors, use for ice40
2022-12-07 16:19:55 +01:00
Sean Anderson
df99b4ff6c ice40: Add debugs to isBelLocationValid for SB_IO
When there is a constraint conflict while placing IOs, the user gets an
error message such as

ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO'

While this identifies the problematic cell, it does not explain why
there is a problem. Add some verbose messages to allow users to
determine where the problem is. This can result in something like

Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin'

which provides something actionable.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-12-07 10:32:38 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:27:58 +01:00
myrtle
519011533a
Merge pull request #1058 from YosysHQ/gatecat/bounds-refactor
refactor: rename ArcBounds -> BoundingBox and use this in HeAP
2022-12-07 10:26:17 +01:00
gatecat
d1afd6c0f1 heap: Remove custom bounding-box type
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:02:16 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:00:53 +01:00
myrtle
a342b96bb0
Merge pull request #1055 from yrabbit/pll-pins
gowin: add PLL pins processing
2022-12-06 21:20:59 +01:00
YRabbit
150a482b77 gowin: change the way networks are handled
Until a comprehensive clock router is developed, the order in which
private cases are handled is important.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-12-06 23:07:01 +10:00
myrtle
cd3b76e3f7
Merge pull request #1056 from YosysHQ/gatecat/generic-fix-consts
viaduct: Fix constant connectivity
2022-12-06 12:27:03 +01:00
gatecat
3a61bb4119 viaduct: Fix constant connectivity
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-06 10:04:59 +01:00
YRabbit
e6a8d0f4fc Merge branch 'master' into pll-pins 2022-12-04 21:33:36 +10:00
myrtle
db25c5c889
Merge pull request #1054 from YosysHQ/gatecat/api-add-const
api: Make NetInfo* of checkPipAvailForNet const
2022-12-04 12:27:53 +01:00
YRabbit
2e68962a02 gowin: add PLL pins processing
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.

The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-12-04 15:06:44 +10:00
gatecat
91454515f4 Unbreak CI
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-02 14:26:13 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-02 14:20:39 +01:00
myrtle
f07d9a1835
Merge pull request #1048 from yrabbit/chipdb-cfg
gowin: add information about pin configurations
2022-12-02 09:58:46 +01:00
YRabbit
b0791a01c9 gowin: update the apicula version
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-12-02 08:49:56 +10:00
YRabbit
7638146782 Merge branch 'master' into chipdb-cfg 2022-12-02 08:28:51 +10:00
myrtle
719f89806a
Merge pull request #1053 from YosysHQ/gatecat/pbfix
ecp5: Fix Python bindings for pip iterators
2022-11-28 09:45:11 +01:00
gatecat
6ee3daf06a ecp5: Fix Python bindings for pip iterators
Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-28 09:00:41 +01:00
YRabbit
ec53ae0c3b gowin: add information about pin configurations
Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-11-25 20:49:26 +10:00
myrtle
c61d490bd4
Merge pull request #1045 from yrabbit/unused-ports
gowin: mark the PLL ports that are not in use
2022-11-20 13:55:01 +01:00
YRabbit
378ca60a2f gowin: mark the PLL ports that are not in use
Unused ports are deactivated by special fuse combinations, rather than
being left dangling in the air.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-11-20 22:04:09 +10:00
myrtle
c8406b71fe
Merge pull request #1042 from yrabbit/add-z1
gowin: add support for a more common chip
2022-11-12 11:17:06 +01:00
YRabbit
d4642d918c gowin: add support for a more common chip
The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-11-12 10:12:43 +10:00
myrtle
1aa9cda77a
Merge pull request #1040 from yrabbit/pll-stage0
gowin: add initial PLL support
2022-11-11 10:28:19 +01:00
YRabbit
9013b2de50 gowin: use ctx->idf() a bit
Replacing snprintf() with ctx->idf() in PLL commit, but not yet a
complete overhaul.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-11-11 09:19:16 +10:00
myrtle
79cb2f9e20
Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warning
Fix "implicit copy constructor for 'Property' is deprecated"
2022-11-10 15:40:50 +01:00
gatecat
8a69bd0735 Fix "implicit copy constructor for 'Property' is deprecated"
Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-10 10:57:41 +01:00
gatecat
6930ab3acd fabulous: Tweak delay estimate
Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-10 10:55:37 +01:00
YRabbit
a84ded4793 gowin: add initial PLL support
The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.

Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-11-10 19:14:41 +10:00
Miodrag Milanović
ac17c36bec
Merge pull request #1037 from YosysHQ/fix_python_ver
Fix python version in CI
2022-10-24 09:45:57 +02:00
Miodrag Milanovic
4ffa47d897 Fix python version in CI 2022-10-24 09:42:16 +02:00
Miodrag Milanovic
010b2e5ecf Update CI script 2022-10-24 09:28:34 +02:00
gatecat
445d32497d run clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2022-10-17 12:35:02 +02:00
myrtle
bd082132ce
Merge pull request #1034 from lushaylabs/support-windows-crlf
Support windows line endings in constraints for nextpnr-gowin
2022-10-17 12:33:33 +02:00
myrtle
c2dbaa2b11
Merge pull request #1035 from tyler274/patch-1
Correct Not Equal operator implementation in ice40
2022-10-17 10:43:34 +02:00
Tyler
613d84fb72
Correct Not Equal operator implementation in ice40
I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
2022-10-17 01:19:51 -07:00
Lushay Labs
a7acda95f0
support windows line endings 2022-10-09 23:47:09 +03:00
myrtle
0d1ea9e6ed
Merge pull request #1032 from davidlattimore/registered-output-xform
nexus: Transform registered output parameters
2022-10-05 11:07:42 +02:00
David Lattimore
1602774d27 nexus: Transform registered output parameters
Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
2022-10-05 14:40:49 +11:00