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Author SHA1 Message Date
gatecat
9b3fb00908 interchange: Initial global routing implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:28:56 +01:00
gatecat
b8c8200683 interchange: Add more global cell info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:25:18 +01:00
gatecat
3144e83950
Merge pull request #697 from YosysHQ/gatecat/router2-dynamic-bb-expand 
router2: Dynamicly expand bounding box based on congestion
 2021-05-06 22:05:04 +01:00
gatecat
65c611da02 router2: Reserve wires in more complex cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 21:20:09 +01:00
gatecat
62613cb266 router2: Dynamicly expand bounding box based on congestion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 19:04:24 +01:00
gatecat
ae8a910339 Revert "nexus: Enable placeAllAtOnce" 
This reverts commit 0abe425675.
 2021-05-06 15:51:54 +01:00
gatecat
c322cda3f8
Merge pull request #688 from YosysHQ/gatecat/new-cluster-api 
New cluster API
 2021-05-06 13:58:08 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
gatecat
c6fa1a179a nexus: Use new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:25:32 +01:00
gatecat
1bf202adcd base_arch: Fix typo in getClusterPlacement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:23:28 +01:00
gatecat
c82df9e40d ecp5: Use new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:59:58 +01:00
gatecat
14863bc04e Update placers to use new cluster APIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:07 +01:00
gatecat
6a3eacddd6 Add default base implementation of cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat
e1717bd771 Add BaseClusterInfo for base implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat
b62dcc4bcc arch_api: Outline of new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat
ed17091e6a
Merge pull request #692 from davidcorrigan714/patch-1 
Fix variable name in bits.h for MSVC builds
 2021-05-01 10:25:00 +01:00
David Corrigan
f5c2547952
Update bits.h 
Fixed the variable name for windows MSVC builds.
 2021-04-30 21:42:25 -05:00
gatecat
4bdf4582f0 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 18:38:30 +01:00
gatecat
3dd8986322
Merge pull request #664 from YosysHQ/gatecat/nexus-counter 
interchange/nexus: Add counter example
 2021-04-30 14:53:30 +01:00
gatecat
49caad0b7b interchange/nexus: Add counter example 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 14:15:37 +01:00
gatecat
0461cc8c3a
Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types 
interchange: Add wire types
 2021-04-30 13:29:21 +01:00
gatecat
5225550b5b interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:42:43 +01:00
gatecat
dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat
ecf24201ec interchange: Add wire types to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:14 +01:00
gatecat
d718ccaa78
Merge pull request #689 from adamgreig/ecp5-alu 
ECP5 ALU54B placement support
 2021-04-29 10:50:28 +01:00
Adam Greig
d3a6cf3ae7
Only set CIBOUT_BYP on MULTs that are not feeding an ALU. 2021-04-29 02:23:45 +01:00
Adam Greig
b6c608e038
Add check_alu to Ecp5Packer 
Checks that every ALU54B is correctly connected to two MULT18X18Ds:

* SIGNEDIA and SIGNEDIB connected to SIGNEDP
* MA and MB connected to P
* A and B connected to {ROA, ROB}

Diamond enforces these requirements; the connections are fixed
in any event so no other connection is possible.
 2021-04-29 02:23:44 +01:00
Adam Greig
d4c688297c
Add relative constraints to position MULT18X18D near connected ALU54B. 2021-04-29 02:23:43 +01:00
Adam Greig
9538954cc6
Add ALU54B.REG_OPCODEOP1_1_CLK parameter support 2021-04-29 02:23:42 +01:00
gatecat
b7bf7c11a8
Merge pull request #685 from YosysHQ/gatecat/nexus-routing 
nexus: Enable placeAllAtOnce
 2021-04-25 12:46:14 +01:00
gatecat
0abe425675 nexus: Enable placeAllAtOnce 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-25 11:53:21 +01:00
gatecat
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword 
interchange: allow LOC keyword in XDC files
 2021-04-20 14:12:14 +01:00
Jan Kowalewski
d1548ed317 interchange: allow LOC keyword in XDC files 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-04-20 14:35:15 +02:00
gatecat
95698827b8
Merge pull request #682 from YosysHQ/gatecat/default-cellpins 
interchange: Handle missing/disconnected cell pins
 2021-04-20 11:33:51 +01:00
gatecat
0e6955a08d interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-20 10:42:33 +01:00
gatecat
18459a9e4c interchange: Handle disconnected/missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:46:35 +01:00
gatecat
872b3aa63d interchange: Add default cell connections to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:16:26 +01:00
gatecat
6fbefb8f13
Merge pull request #681 from YosysHQ/gatecat/more-pybindings 
Add Python bindings for placement tests
 2021-04-15 11:16:31 +01:00
gatecat
1631cdffb8
Merge pull request #680 from YosysHQ/gatecat/fix-util 
Fix utilisation report when bel buckets are used
 2021-04-15 10:14:19 +01:00
gatecat
d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat
d14db5c98f Fix utilisation report when bel buckets are used 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 09:24:27 +01:00
gatecat
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi
ea9e12b6ae gh-actions: increase python-fpga-interchange tag version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:47 +02:00
Alessandro Comodi
dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat
b26088f940
Merge pull request #679 from YosysHQ/gatecat/disable-absl 
Hash table changes
 2021-04-14 12:19:10 +01:00
gatecat
b0f57d234f ci: Re-enable abseil for interchange CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:53 +01:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
2912860c97
Merge pull request #677 from YosysHQ/gatecat/ppip-no-input 
interchange: Allow pseudo-cells with no input pins
 2021-04-13 11:49:48 +01:00
gatecat
06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat
423da76ff2
Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash 
timing: Fix domain init when loops are present
 2021-04-13 10:34:14 +01:00