gatecat
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d89afc2aa6
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ci: Enable -Werror for interchange arch
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-09-28 09:42:25 +01:00 |
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Alessandro Comodi
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721e760f1a
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ci: remove RapidWright patching
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-06-24 08:23:59 +02:00 |
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Alessandro Comodi
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aa1784c5d9
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interchange: ci: add RW patch for missing cell bel maps
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-06-11 11:49:59 +02:00 |
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gatecat
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dcbb322447
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Remove redundant code after hashlib move
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-02 15:05:20 +01:00 |
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gatecat
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0426ba4e87
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interchange: Add LIFCL-40 EVN tests
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-01 09:52:40 +01:00 |
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gatecat
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b0f57d234f
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ci: Re-enable abseil for interchange CI
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-04-14 10:30:53 +01:00 |
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gatecat
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7acef00443
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interchange: Pin prjoxide commit
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-04-09 11:17:25 +01:00 |
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Keith Rothman
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3a85088d66
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[interchange] Update interchange CI for new chipdb change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2021-04-01 15:59:48 -07:00 |
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gatecat
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3678eff5dc
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interchange: Fix nexus cmake review comments
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-03-31 10:11:09 +01:00 |
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gatecat
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9259763599
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ci: Build prjoxide only for LIFCL
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-03-30 16:55:03 +01:00 |
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gatecat
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b6b8959397
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interchange: Add Nexus to CI
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-03-30 16:31:51 +01:00 |
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Alessandro Comodi
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d0bc033ab8
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gh-actions: better yosys caching based on version
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-26 15:11:03 +01:00 |
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Alessandro Comodi
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c4cb86efe9
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gh-actions: use ccache and build tools before running tests
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-25 16:24:52 +01:00 |
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Alessandro Comodi
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9f28fa4e75
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gh-actions: interchange: multiple jobs, one for each device
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-24 15:37:03 +01:00 |
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Keith Rothman
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720f64ea60
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[FPGA interchange] Add support for global buffers from chipdb.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2021-03-23 09:41:45 -07:00 |
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Keith Rothman
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8a50b02b9b
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Use new parameter definition data in FPGA interchange processing.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2021-03-23 09:01:43 -07:00 |
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Keith Rothman
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694f9ec3a5
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Increment required python-fpga-interchange version.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2021-03-22 09:33:12 +00:00 |
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Alessandro Comodi
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f9e9fadbc8
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github-actions: use capnp v0.8.0
This also updates the note in the README for the FPGA interchange
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-16 16:57:07 +01:00 |
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Alessandro Comodi
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83544cdf6a
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github-actions: pin python-fpga-interchange to tag
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-16 16:34:27 +01:00 |
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Alessandro Comodi
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c68dfb09c4
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github-actions: add basic CI to test FPGA interchange
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-03-16 15:39:02 +01:00 |
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