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1113 Commits

Author SHA1 Message Date
gatecat
326b34887c
Merge pull request #609 from YosysHQ/gatecat/sta-v2 
Use new timing engine for criticality
 2021-03-09 08:48:12 +00:00
gatecat
da88d3d825 router2: Fix vast perf drop when leaving bounding box 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:06:30 +00:00
gatecat
8a4bf3a780 timing: Integration tweaks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 10:04:35 +00:00
gatecat
98d1c5a411 timing: Skip route delays for unplaced/nullptr cells 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:34:20 +00:00
gatecat
1ff2023f32 timing: Replace all users of criticality with new engine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:29:11 +00:00
gatecat
5f6aaa2475 timing: Use new engine in SA except for budget-based mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
ebc2527368 timing: Use new engine for HeAP 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
bbf5a7d461 timing: Add support for critical path printing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
e681e0f14c timing: Slack and criticality computation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
296e6d10c2 timing: Produce plausible Fmax figure 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
541376f8cc timing: Add Fmax printing for debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
16e7bba87b timing: Add backwards path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
0528ceead1 timing: Add forward path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
9c8d1bd6e3 timing: Compute domain pairs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
534e69fbff timing: Add port-domain tracking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
7a546b1554 timing: Add topological sort from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
d0772ce1e3 timing: Import cell delays to our own structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
fac6a6c068 timing: Data structures for STA rewrite 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
6e38e236f8
Merge pull request #604 from litghost/add_counter_test 
Add counter test for FPGA interchange
 2021-03-03 07:06:07 +00:00
gatecat
27fbee5233
Merge pull request #605 from litghost/add_placement_sanity_check 
Add placement sanity check in placer_heap.
 2021-03-02 08:27:12 +00:00
Keith Rothman
392156c250 Correct spelling of RAII and add missing check in unlock_early. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 13:11:04 -08:00
Keith Rothman
0afa0da19f Add absl::flat_hash_map. 
This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:55:54 -08:00
Keith Rothman
99a2262d61 Use scope in router1/2 and placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:43:39 -08:00
Keith Rothman
77a5a60a66 Fix latent bug with context locking in placer HeAP. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:40:58 -08:00
Keith Rothman
7878561970 Add placement sanity check in placer_heap. 
Also check return of placer1_refine.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:27:43 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
c65ba121e0 Prevent trival misplacements in placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 10:59:48 -08:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API 
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-26 10:07:00 +00:00
Keith Rothman
c64a910151 Allow router2 to use routed but not fixed arcs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-25 15:55:29 -08:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
ab8dfcfba4
Merge pull request #591 from litghost/add_constant_network 
Add constant network support to FPGA interchange arch
 2021-02-25 10:22:45 +00:00
gatecat
e2cdaa653c
Merge pull request #597 from litghost/add_dynamic_bitarray 
Add dynamic bitarray to common library.
 2021-02-24 18:22:16 +00:00
Keith Rothman
6d193ffd8b Fix some bugs found in review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:06 -08:00
Keith Rothman
3650294e51 Add dynamic bitarray to common library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 15:43:47 -08:00
gatecat
19ae97afd1
Merge pull request #595 from litghost/const_cell_info 
Change CellInfo in getBelPinsForCellPin to be const.
 2021-02-23 22:55:09 +00:00
gatecat
5de1978632
Merge pull request #596 from litghost/make_clang_format 
Run "make clangformat" to fix formatting in new Bits library.
 2021-02-23 22:49:35 +00:00
Keith Rothman
5c6e231412 Remove some signedness warnings. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
Keith Rothman
bf458cbc5a Run "make clangformat" to fix new Bits library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 13:55:05 -08:00
gatecat
162793aa87 Refactor some common code to CellInfo methods 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
72b7a2e107 HeAP: Document legalise_placement_strict better 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
c0a7cff304 Demote the 'no clocks' warning to info and make clearer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 20:15:52 +00:00
gatecat
6672f17d0a
Merge pull request #592 from YosysHQ/gatecat/rework-delay 
Replace DelayInfo with DelayPair and DelayQuad
 2021-02-20 10:51:57 +00:00
gatecat
130c5cc768 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:52:06 +00:00
gatecat
8ab36b4a05 python: Bindings for DelayPair and DelayQuad 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:41:40 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
8376db94a7 Add DelayPair and DelayQuad structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 10:58:16 +00:00
gatecat
5dcb59b13d
Merge pull request #576 from litghost/add_cell_bel_pin_mapping 
Complete FPGA interchange Arch to the point where it can route a wire
 2021-02-19 08:41:58 +00:00
Balint Cristian
456688a49d Expose ice40 arch placer-heap internal parameters. 2021-02-18 00:06:23 +02:00
Keith Rothman
8f668f06ca Use Bits library for bit instrisics. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
e189666a2d Add a Bits utility library. 
This library captures use of __builtin_popcount and __builtin_ctz on
GCC/clang and hopefully handles the MSVC case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 11:00:39 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
gatecat
cede682585
Merge pull request #579 from litghost/add_control_for_split_io 
Add control to whether GenericFrontend splits IO ports.
 2021-02-12 18:22:06 +00:00
gatecat
c956cae824 Make BaseArch getDecalGraphics return an empty range 
Fix assertion failure when opening the GUI on an arch without any
decals.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:35:51 +00:00
gatecat
ad7bb51030
Merge pull request #580 from litghost/add_design_loaded_state_variable 
Add design_loaded state variable.
 2021-02-12 09:54:15 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 14:58:02 -08:00
Keith Rothman
96293ab25e Add design_loaded state variable. 
This is to decouple the command line flag "--json" and enable other
frontend's.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 13:43:23 -08:00
Keith Rothman
73710416b4 Add control to whether GenericFrontend splits IO ports. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 13:33:55 -08:00
gatecat
7c7d69e1d2 router2: Support for multiple bel pins per cell pin 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 15:14:44 +00:00
gatecat
7dafc64f78 router1: Support for multiple bel pins per cell pin 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 14:46:03 +00:00
gatecat
535723f414 Start making use of getBelPinsForCellPin API 
This replaces getNetinfoSinkWire with 3 new functions for different use
cases.

At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 14:18:12 +00:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API 
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 11:54:54 +00:00
gatecat
6bd3dba1e3 Remove the unused CellInfo::pins field 
No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.

This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 10:42:26 +00:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-09 10:39:14 +00:00
gatecat
2932dc3985 Make BaseCtx destructor virtual 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-08 17:03:22 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using 
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
59c3db46ca ice40: Switch to BaseArch 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
a8a27299ae Add pure-virtual ArchAPI interface 
This splits out the pure-virtual definition of the architecture API into
ArchAPI; leaving BaseArch to only provide default implementations (which
can now be completely opted out of by deriving from ArchAPI instead of
BaseArch).

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
b4227f586c Rename ArchBase to BaseArch for consistency with BaseCtx 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
297cd026b9 Add default implementation of bel bucket functions 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
ed8e3c83d9 Add default implementation of some range-returning functions 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
6d794abf49 Add a few more functions to ArchBase 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
d4363b7ee5 ecp5: Use common wire/pip binding 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
b866601b63 Fix now-illegal use of reinterpret_cast 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
ba5568d501 nextpnr: Example of shared wire/bel/pip binding code 
Currently not actually being tested

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
cfa9a9daec nextpnr: Use templates to specify range types 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
8f76af40db nextpnr: Add base virtual functions for non-range Arch API 
This makes the Arch API clearer and also allows a base implementation of
functions to reduce the amount of complexity to get a basic Arch up and
running.

Currently this only implements these for functions that don't return a
range. Range-returning functions will require more work in order due to
the current 'duck typing' approach (probably a struct that contains the
range types combined with templating.)

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
Keith Rothman
a0ee42833b Add RelSlice::ssize and use it when comparing with signed ints. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-05 10:12:13 -08:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit. 
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:07 -08:00
Keith Rothman
235a8e07e3 Use a LRU cache for pip to wire map. 
This avoids storing the entire pip to wire map in memory with a moderate
runtime increase and a dramatic memory decrease (2 GB to 200 MB for
A50T).

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-03 13:45:47 -08:00
D. Shah
7cff69f945 generic: Use IdStringList for all arch object names 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:56 +00:00
D. Shah
6566a011b4 nexus: Implement IdStringList for all arch object names 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:33 +00:00
D. Shah
d792bce0fb ecp5: Implement IdStringList for all arch object names 
This is a complete implementation of IdStringList for ECP5; excluding
the GUI (which you will have to disable for it to build).

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:32 +00:00
D. Shah
9388df19d3 refactor: Replace getXName().c_str(ctx) with ctx->nameOfX 
This makes the ongoing migration to IdStringList easier.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:14 +00:00
D. Shah
6d23461bcd ecp5: Proof-of-concept using IdStringList for bel names 
This uses the new IdStringList API to store bel names for the ECP5. Note
that other arches and the GUI do not yet build with this
proof-of-concept patch.

getBelByName still uses the old implementation and could be more
efficiently implemented with further development.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:12 +00:00
D. Shah
0dbe7f96a3 common: First pass at IdStringList methods 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 16:59:42 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 16:59:40 +00:00
D. Shah
90edf33c95 common: Adding IdStringList type 
Using an optimised storage for <=4 objects to avoid excessive heap
allocations.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 16:58:57 +00:00
Keith Rothman
da74a425d2 Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:44:49 -08:00
Keith Rothman
1deab29b05 Moving missing empty check into initial placement loop. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:43:38 -08:00
Keith Rothman
9089ee2d16 Add pybindings for new APIs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:43:36 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
8d9390fc46 Fix regression in use of FastBels. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
16394d3158 Address some compiler warnings. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
d03d9d839b Working compile of ECP5. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
878fcdd22d Implement partitioning in placer_heap. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
b4160c228e Add archcheck for partition methods. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
David Shah
efc98c517e
Merge pull request #563 from litghost/seperate_pip_range_types 
Seperate PipRange types in pybindings_shared.
 2021-02-02 09:59:18 +00:00
Keith Rothman
5cf2f8d1ea Seperate PipRange types in pybindings_shared. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-01 10:23:21 -08:00
Keith Rothman
b8c823ef99 Avoid linear scan in PIP check loop. 
The previous additions to archcheck increased the runtime of the nexus
archcheck quiet a bit.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-01-29 13:42:14 -08:00
D. Shah
94e8847d67 cleanup: Spelling fixes 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 15:19:06 +00:00
D. Shah
5fc3e8e4d2 cleanup: Fix compiler warnings 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 15:02:08 +00:00
D. Shah
6ecf7f86c8 cleanup: Remove dead/unused code 
Note that some '#if 0' code that might still be useful for debugging in
the future has been retained.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 14:59:13 +00:00
D. Shah
0d97904216 clangformat 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 14:38:20 +00:00
David Shah
b671d8f59d
Merge pull request #553 from YosysHQ/rel-slice 
Switch from RelPtr to RelSlice
 2021-01-28 12:53:03 +00:00
Keith Rothman
b8770915ad Add connectivity round trip checks to archcheck. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-01-27 18:14:09 -08:00
D. Shah
b87ab0ee9d Make RelSlice uncopyable 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 20:49:14 +00:00
D. Shah
75ee2fc4e6 Move RelPtr/RelSlice out of arches into common 
The bba approach seems widely used enough that it's reasonable for this
to become part of common code.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 20:43:01 +00:00
Per Grön
60276e3447 C++17 compatibility: Don't use std::random_shuffle 
std::random_shuffle deprecated in C++14 and was removed in C++17.
 2020-12-30 18:53:32 +01:00
Pepijn de Vos
3611f54902
Gowin target (#542) 
* load wires

* add slice bels

* add IOB

* add aliases

* local aliases

* broken packing stuff

* working packer

* add constraints

* pnr runs1111

* add timing info

* constraints

* more constraint stuff

* add copyright

* remove generic reference

* remove parameters

* remove generic python api

* add newline to end of file

* some small refactoring

* warn on invalid constraints

* don't error on missing cell

* comment out debugging print

* typo

* avoid copy

* faster empty idstring

* remove intermediate variable

* no more deadnames

* fix cst warnings

* increase ripup and epsilon a bit

* take single device parameter

* add info to readme

* gui stubs

* Revert 4d03b681a8

* assign ff_used in assignArchInfo

* decrease beta for better routability

* try to fix CI
 2020-12-30 14:59:55 +00:00
David Shah
a40829fef3 command.cc: Improve help text 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-27 20:05:33 +00:00
David Shah
402819c64b router2: Avoid ripup of critical path 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-01 09:54:19 +00:00
David Shah
3503f4e907 router2: Make splitting of wires thread-safe 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-01 09:38:52 +00:00
David Shah
b6c91d1621 router2: Add per-thread rng 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-01 09:21:44 +00:00
David Shah
d8e748bc58 nexus: Refactor DSP macro splitting to make it more generic 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
30c65931b2 nexus: Add support for clocked MULT9X9s 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
9203181625 nexus: Support for unclocked 9x9 multiplies 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
094bf419d4 nexus: Miscellaneous DSP infrastructure 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
90608f2c89 nexus: Add some infrastructure for DSP packing 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
a69c595802 router1: Fix same-source-dest case 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
5e90086d4f router2: Fix case where src and dst are the same 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
cbf99d5e53 nexus: LUTRAM support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
1bb509897c nexus: More pin styles and FASM pinmux gen 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
518ead2e2d nexus: IO pre-packing 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
84d5426242 nexus: Working on validity checking 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
b5d46a0235 nexus: Add Python bindings 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
44f98c545b nexus: Add global networks 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah
1afa494e69 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-26 18:08:19 +00:00
David Shah
70de8b3a03 nextpnr: Improve error reporting in Context::check 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-26 11:12:20 +00:00
Miodrag Milanovic
bb16fdb4bb Python code cleanup 2020-11-14 16:34:12 +01:00
David Shah
06555aa003 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-14 09:07:34 +00:00
David Shah
b18ea204c2 Remove wire alias API 
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink.

Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 09:36:15 +01:00
Miodrag Milanović
f7da7c26aa
Merge pull request #500 from YosysHQ/dave/py-none-fix 
python: Fix handling of None in pybind11
 2020-09-14 15:57:29 +02:00
David Shah
b5e5f8d85f python: Fix handling of None in pybind11 
Signed-off-by: David Shah <dave@ds0.me>
 2020-09-14 14:17:07 +01:00
Miodrag Milanovic
717bcfa19e Preserve cmd parameters when loading json from GUI 2020-09-04 17:14:30 +02:00
Ross Schlaikjer
c30cadd19c
No longer need fstream include 2020-08-30 18:22:05 -04:00
Ross Schlaikjer
cba4753c22
Only print filenames for now, default on 2020-08-30 18:19:41 -04:00
Ross Schlaikjer
a8c110b045
Add option to print critical path source code 
In order to make debugging the critical path easier, add an option that
will log the location each net was defined, if known.
If the file that contains the definition is known, and is readable, also
print the part of the source HDL responsible for the signal definition.
 2020-08-30 17:43:29 -04:00
David Shah
109aa63474 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-08-20 09:46:49 +01:00
David Shah
b0dedf1a22
Merge pull request #488 from YosysHQ/dave/port_fanin_fix 
timing: Fix counting of fanin in out-of-context mode
 2020-08-12 16:38:46 +01:00
David Shah
3611b7120c timing: Fix counting of fanin in out-of-context mode 
Signed-off-by: David Shah <dave@ds0.me>
 2020-08-12 10:42:26 +01:00
David Shah
e313d051a8 Add a warning when floorplan constraint doesn't match 
Signed-off-by: David Shah <dave@ds0.me>
 2020-08-12 10:11:52 +01:00
Miodrag Milanovic
1168d1ff90 Made proper exception translation 2020-08-07 09:46:02 +02:00
Miodrag Milanovic
fe398ab983 clangformat 2020-07-25 10:17:13 +02:00